Semiconductor device having a stressor film

1. A semiconductor device comprising an NMIS transistor over a first active region of a semiconductor substrate, the NMIS transistor including:

a first gate dielectric film over the first active region;

a first gate electrode on the first gate dielectric film;

a first side-wall dielectric film on side surfaces of the first gate dielectric film and the first gate electrode;

a first source/drain region in the first active region outside the first side-wall dielectric film;

a first silicide layer in a top-layer portion of the first source/drain region;

a second side-wall dielectric film formed on the first silicide layer to cover around a corner at which the side surface of the first side-wall dielectric film meets an upper surface of the first silicide layer; and

a first stressor film for exerting a tensile stress on a channel region in a gate length direction, the first stressor film covering the first gate electrode, the first side-wall dielectric film, and the second side-wall dielectric film,

wherein the first stressor film is not in contact with a surface of the corner at which the side surface of the first side-wall dielectric film meets the upper surface of the first silicide layer.

2. The semiconductor device of claim 1 , wherein the second side-wall dielectric film is lower in height than the first side-wall dielectric film.

3. The semiconductor device of claim 1 , wherein a material of at least the side surface of the first side-wall dielectric film is different from a material of the second side-wall dielectric film.

4. The semiconductor device of claim 1 , wherein the first side-wall dielectric film is composed of:

a first dielectric film being in contact with the side surface of the first gate electrode and having an L-shaped cross section; and

a first side-wall on an inner surface of the first dielectric film.

5. The semiconductor device of claim 1 , wherein the first stressor film is formed of a silicon nitride film or a silicon nitride film containing hydrogen.

6. The semiconductor device of claim 1 , wherein the first stressor film has no slit formed around the corner at which the side surface of the first side-wall dielectric film meets the upper surface of the first silicide layer.

7. The semiconductor device of claim 1 , further comprising a PMIS transistor over a second active region in the semiconductor substrate, the second active region being different from the first active region, the PMIS transistor including:

a second gate dielectric film over the second active region;

a second gate electrode on the second gate dielectric film;

a third side-wall dielectric film on side surfaces of the second gate dielectric film and the second gate electrode;

a second source/drain region in the second active region outside the third side-wall dielectric film;

a second silicide layer in a top-layer portion of the second source/drain region;

a second stressor film for exerting a compressive stress on a channel region in a gate length direction, the second stressor film covering the second gate electrode and the third side-wall dielectric film.

8. The semiconductor device of claim 7 , wherein the second side-wall dielectric film and the second stressor film are formed of the same dielectric film.

9. The semiconductor device of claim 7 , wherein no side-wall dielectric film is provided around a corner at which a side surface of the third side-wall dielectric film meets an upper surface of the second silicide layer.

10. The semiconductor device of claim 1 , wherein the second side-wall dielectric film is in contact with the first silicide layer.

11. The semiconductor device of claim 1 , wherein a bottom surface of the second side-wall dielectric film is in contact with the upper surface of the first silicide layer.

12. The semiconductor device of claim 4 , wherein the second side-wall dielectric film covers a side-wall of the first dielectric film located between an upper surface of the first active region and a bottom surface of the first side wall.

13. The semiconductor device of claim 4 , wherein the first stressor film is not in contact with the side wall of the first dielectric film located between an upper surface of the first active region and a bottom surface of the first side wall.