Method and apparatus providing column parallel architecture for imagers
View Patent ↗An imaging apparatus and a method using column processing circuits arranged in multiple rows for processing pixels in a pixel array.
1. An imager comprising:
an array of pixels arranged in a plurality of rows and a plurality of columns,
a first array of processing circuits adjacent a first edge of the array of pixels, each of said processing circuits being coupled to receive pixel signals from a column of said array,
wherein the first array of processing circuits comprises n rows of processing circuits, where n>1, and
wherein each row of processing circuits in the first array of processing circuits comprises processing circuits satisfying:
P
≥
(
C
+
d
)
n
,
wherein P represents the average width of all pixels in the pixel array, C represents the average width of the processing circuits in the row, d represents the average distance between processing circuits in the row, and n represents the number of rows in the first array of processing circuits.
2. An imager comprising:
an array of pixels arranged in a plurality of rows and a plurality of columns,
a first array of processing circuits adjacent a first edge of the array of pixels, each of said processing circuits being coupled to receive pixel signals from a column of said array,
wherein the first array of processing circuits comprises n rows of processing circuits, where n>1, and
wherein the imager further comprises a second array of processing circuits, wherein the second array of processing circuits comprises m rows of processing circuits, where m>1, each of said processing circuits in said m rows comprising an analog-to-digital converter, each being coupled to receive pixel signals from a column of said array, and each row of processing circuits in the first array and second array comprising processing circuits satisfying:
P
≥
(
C
+
d
)
m
+
n
wherein P represents the average width of all pixels in the pixel array, C represents the average width of all analog-converters in the first array and second array, d represents the average distance between all adjacent processing circuits in all rows.