Timer circuit storing a plurality of time measurements with different sets of measurement time that can be realized by starting the time measurements asynchronously

1. A timer circuit, comprising:

a counter that operates under a reference clock;

a storage unit that stores a timer timeout time corresponding to a time measurement request when receiving the time measurement request from a CPU; and

a comparator that compares the time corresponding to an output value of the counter with the timer timeout time stored in the storage unit, and outputs an interruption signal to the CPU when both the two sets of time are coincident with each other;

wherein the storage unit includes:

a first memory that stores a plurality of sets of timer timeout time corresponding to a plurality of time measurement requests; and

a second memory that stores, of the plural sets of timer timeout time stored in the first memory, at least the timer timeout time which is closest to the time corresponding to the output value of the counter and the timer timeout time stored in the second memory is set to the timer timeout time to be compared by the comparator,

wherein the first memory stores enable information to set up whether the plural sets of timer timeout time are enable or disable, and enable information of the corresponding timer timeout time is set to be disable when an interruption signal is generated by the comparator, and the second memory stores the timer timeout time whose enable information is set to be enable, and

wherein the first memory stores carry out information which indicates whether or not the counter is carried out, and the timer timeout time is updated based on the carry out information when the counter is carried out.

2. The timer circuit according to claim 1 , wherein the storage unit includes:

sort means for rearranging the plural sets of timer timeout time stored in the first memory in the order ranging from the time closest to the time corresponding to the output value of the counter; and

setup means for setting up the plural sets of timer timeout time sorted by the sort means in the second memory.

3. The timer circuit according to claim 1 , wherein the second memory stores only the timer timeout time which is closest to the time corresponding to the output value of the counter.

4. The timer circuit according to claim 1 , wherein the second memory is updated when the plural sets of timer timeout time stored in the first memory are updated.

5. A mobile communication terminal that has a timer circuit according to claim 1 .

6. An electronic device that has a timer circuit according to claim 1 .