Patterning metal layers
View Patent ↗A process for fabricating an electronic device comprising the step of patterning a metallic electrode to the electronic device by laser ablation followed by electroless plating, wherein the process of fabricating the electronic device comprises at least one other laser patterning step over the area of the metallic electrode performed after said step of patterning the metallic electrode.
1. A method of producing one or more semiconductor devices, including the steps of: (i) forming an initial metal layer on a substrate; (ii) ablating selected portions of the metal layer using laser pulses each of an energy sufficient to ablate the entire thickness of the initial metal layer so as to pattern the initial metal layer; (iii) selectively depositing metal on the remaining portions of the patterned metal layer so as to form a patterned metal layer of increased thickness; and (iv) providing a semiconductor or another conductor layer over the patterned metal layer of increased thickness for interaction with the patterned metal layer in the one or more semiconductor devices.
2. A method according to claim 1 , further comprising the step of selectively ablating portions of the semiconductor or another conductor layer over the patterned metal layer of increased thickness using laser pulses of energy less than would be required to ablate the entire combined thickness of the semiconductor or another conductor layer and patterned metal layer of increased thickness, but more than would be required to ablate the entire combined thickness of the semiconductor layer and the initial metal layer if the semiconductor layer were formed directly on the initial metal layer.
3. A method of producing a plurality of semiconductor devices according to claim 1 , wherein the patterned metal layer defines one or more metal electrodes for each of the plurality of semiconductor devices and also defines one or more interconnects connecting electrodes of one or more the plurality of semiconductor devices.
4. A method according to claim 1 , wherein the patterned metal layer defines source and drain electrodes for each of the one or more semiconductor devices.
5. A method according to claim 1 , wherein the step of selectively depositing metal on the remaining portions of the patterned metal layer comprises a first sub-step of selectively depositing a first metal on the remaining portions of the patterned metal layer and then selectively depositing a second metal on the first metal.
6. A method according to claim 1 , wherein the step of selectively depositing metal on the remaining portions of the patterned metal layer is carried out by electroless plating.
7. A method according to claim 1 , wherein the thickness of the initial metal layer is about 10 nm or less.
8. A method according to claim 1 , wherein the metal selectively deposited on the remaining portions of the patterned layer is a different metal as that of the initial metal layer.
9. A method according to claim 5 , wherein the second metal layer has a different workfunction than the first metal layer.
10. A method of patterning a further semiconductor or conductor layer provided over a patterned metal layer, the method comprising the steps of: (i) forming an initial metal layer on a substrate; (ii) ablating selected portions of the metal layer using laser pulses each of an energy sufficient to ablate the entire thickness of the initial metal layer so as to pattern the metal layer; (iii) selectively depositing metal on the remaining portions of the patterned metal layer so as to form a patterned metal layer of increased thickness; (iv) forming said further layer on the patterned metal layer of increased thickness; (v) selectively ablating portions of said further layer over the remaining portions of the patterned metal layer using laser pulses each of energy less than would be required to ablate the entire combined thickness of said further layer and patterned metal layer of increased thickness, but more than would be required to ablate the entire combined thickness of said further layer and the initial metal layer if the further layer were formed directly on the initial metal layer.
11. A method as claimed in claim 10 , comprising the additional step of depositing a dielectric layer in between said patterned metal layer and said further layer.
12. A method as claimed in claim , 10 wherein said further semiconductor layer comprises an organic semiconductor.