IP Library Granted Patent US 7,680,622
Granted Patent B2
US 7,680,622 · App. 11/911,324 · Granted Mar 16, 2010

Protection of an integrated circuit and method thereof

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Quick Facts
Patent No.
US 7,680,622
App. No.
11/911,324
Granted
Mar 16, 2010
Kind
B2
Abstract

An integrated circuit comprises a power device located on a die. The power device is operably coupled to a processing function, wherein the signal processing function is operably coupled to two or more temperature sensors. A first temperature sensor is operably coupled to the power device to measure a temperature of the power device and the second temperature sensor is located, such that it measures a substantially ambient temperature related to the die. The signal processing function determines the temperature gradient therebetween.

Claims (46)

1. An integrated circuit comprising:

a power device located on a die;

a processing function operably coupled to the power device, wherein the processing function is operably coupled to two or more temperature sensors wherein a first temperature sensor is operably coupled to the power device to measure a temperature of the power device and the second temperature sensor is located such that it measures a substantially ambient temperature related to the die and the processing function determines the temperature gradient therebetween; and

a counter, operably coupled to the processing function and arranged to count a number of times that the determined temperature gradient exceeds a threshold value.

2. An integrated circuit according to claim 1 , wherein the second temperature sensor is operably coupled to a non-high power device or die.

3. An integrated circuit according to claim 1 , wherein the power device is a silicon switch.

4. An integrated circuit according to claim 1 wherein the processing function is a digital circuit and in response to the digital circuit determining the temperature gradient between the power device and an ambient temperature, the digital circuit implements a protection process to protect the power device.

5. An integrated circuit according to claim 4 wherein the processing function is operably coupled to a logic gate driver and the protection process comprises switching off the power device by the logic gate driver or reducing the power applied thereto.

6. An integrated circuit according to claim 5 , wherein the second temperature sensor is operably coupled to a non-high power device or die.

7. An integrated circuit comprising:

a power device located on a die;

a processing function operably coupled to the power device, wherein the processing function is operably coupled to two or more temperature sensors wherein a first temperature sensor is operably coupled to the power device to measure a temperature of the power device and the second temperature sensor is operably coupled to a non-high power device or die and is located such that it measures a substantially ambient temperature related to the die and the processing function determines the temperature gradient therebetween, wherein the non-high power device or die is a control die.

8. An integrated circuit according to claim 7 , further comprising a counter, operably coupled to the processing function and arranged to count a number of times that the calculated temperature gradient exceeds a threshold value.

9. The integrated circuit according to claim 7 wherein the die and the control die are in a dual die arrangement.

10. An integrated circuit according to claim 7 , wherein the power device is a silicon switch.

11. An integrated circuit according to claim 10 , further comprising a counter, operably coupled to the processing function and arranged to count a number of times that the calculated temperature gradient exceeds a threshold value.

12. An integrated circuit according to claim 7 wherein the processing function is a digital circuit and in response to the digital circuit determining the temperature gradient between the power device and an ambient temperature, the digital circuit implements a protection process to protect the power device.

13. An integrated circuit according to claim 12 wherein the processing function is operably coupled to a logic gate driver and the protection process comprises switching off the power device by the logic gate driver or reducing the power applied thereto.

14. An integrated circuit according to claim 13 , further comprising a counter, operably coupled to the processing function and arranged to count a number of times that the calculated temperature gradient exceeds a threshold value.

15. A method of improving a reliability of an integrated circuit comprising a power device, the method comprising the steps of:

measuring a first temperature of the power device;

measuring a second ambient temperature associated with the power device, wherein the step of a measuring a second ambient temperature associated with the power device comprises measuring an ambient temperature of an associated non-high power die,

calculating a temperature gradient between the power device and the non-high power die in response to the steps of measuring;

determining whether the calculated temperature gradient has exceeded a threshold; and

implementing a power reduction process applied to the power device if the temperature gradient exceeds a threshold.

16. A method according to claim 15 , further comprising:

incrementing a counter if the determined temperature gradient exceeds a threshold;

determining whether the Counter has exceeded a threshold;

implementing a power reduction process applied to the power device if the Counter exceeded a threshold.

17. The method of claim 15 wherein the non-high power die is an associated control die.

18. A method of improving a reliability of an integrated circuit comprising a power device, the method comprising the steps of:

measuring a first temperature of the power device;

measuring a second ambient temperature associated with the power device;

calculating a temperature gradient across a portion of the power device in response to the steps of measuring;

determining whether the calculated temperature gradient has exceeded a threshold;

implementing a power reduction process applied to the power device if the temperature gradient exceeds a threshold,

incrementing a counter if the determined temperature gradient exceeds a threshold;

determining whether the Counter has exceeded a threshold; and

implementing a power reduction process applied to the power device if the Counter exceeded threshold.

19. An integrated circuit comprising:

a power device located on a die; and

a processing function operably coupled to the power device, wherein the processing function is operably coupled to two or more temperature sensors wherein a first temperature sensor is operably coupled to the power device to measure a temperature of the power device and the second temperature sensor is located such that it measures a substantially ambient temperature related to the die and the processing function determines the temperature gradient therebetween;

wherein the processing function is a digital circuit and in response to the digital circuit determining the temperature gradient between the power device and an ambient temperature, the digital circuit implements a protection process to protect the power device;

wherein the second temperature sensor is operably coupled to a non-high power device or die.

20. An integrated circuit according to claim 19 wherein the processing function is operably coupled to a logic gate driver and the protection process comprises switching off the power device by the logic gate driver or reducing the power applied thereto.

21. An integrated circuit according to claim 19 further comprising a counter, operably coupled to the processing function and arranged to count a number of times that the calculated temperature gradient exceeds a threshold value.

Assignments (37)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Sep 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Sep 1, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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SECURITY AGREEMENT Recorded Jul 11, 2008
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To: CITIBANK, N.A.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2007
From: DUPUY, PHILIPPE; GUILLOT, LAURENT; MOREAU, ERIC; TURPIN, PIERRE
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