IP Library Granted Patent US 8,552,734
Granted Patent B2
US 8,552,734 · App. 11/911,732 · Granted Oct 8, 2013

Test prepared integrated circuit with an internal power supply domain

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Quick Facts
Patent No.
US 8,552,734
App. No.
11/911,732
Granted
Oct 8, 2013
Kind
B2
Abstract

The integrated circuit ( 10 ) has an internal power supply domain with a power supply voltage adaptation circuit ( 14 ) to adapt the power supply voltage in the power supply domain. Typically, a plurality of such domains is provided wherein the power supply voltage can be adapted independently. During testing an internal power supply voltage is supplied to a temporally integrating analog to digital conversion circuit ( 16 ) in the integrating circuit ( 10 ). A temporally integrated value of the power supply voltage is measured during a measurement period. Preferably, integrating measurements of a plurality of internal supply voltages are performed in parallel during the same measurement time interval. Preferably a further test is performed by changing over between mutually different supply voltages during a further measurement period. In this way the measured integrated supply voltage can be used to check the speed of the change over between the different voltages.

Claims (31)

1. A test prepared integrated circuit with an internal power supply domain, the integrated circuit comprising; an internal power supply conductor for said power supply domain; a power supply voltage adaptation circuit, for selectably adapting a power supply voltage on the internal power supply conductor; a test output; an integrating analog to digital conversion circuit with an input coupled to the power supply conductor and an output coupled to the test output.

2. A test prepared integrated circuit according to claim 1 , comprising a plurality of power supply domains, with respective internal power supply conductors, power supply voltage adaptation circuits and integrating analog to digital conversion circuits for each power supply domain or groups of power supply domains, and a common control input arranged to control start of integration in each of the integrating analog to digital conversion circuits collectively.

3. A test prepared integrated circuit according to claim 1 , comprising a scan chain with a scan output coupled to the test output, the output of the integrating analog to digital conversion circuit being coupled to the test output via the scan chain.

4. A test prepared integrated circuit according to claim 1 , wherein the integrating analog to digital conversion circuit comprises a voltage controlled oscillator with a frequency control input coupled to the power supply conductor and an oscillator output, a counter with an input coupled to the oscillator output and a count output coupled to the test output.

5. A test prepared integrated circuit with an internal power supply domain, comprising:

an internal power supply conductor for said power supply domain; a power supply voltage adaptation circuit, for selectably adapting a power supply voltage on the internal power supply conductor; a test output; an integrating analog to digital conversion circuit with an input coupled to the power supply conductor and an output coupled to the test output;

a plurality of power supply domains, with respective internal power supply conductors, power supply voltage adaptation circuits and integrating analog to digital conversion circuits for each power supply domain or groups of power supply domains, and a common control input arranged to control start of integration in each of the integrating analog to digital conversion circuits collectively;

a plurality of power supply domains, with respective internal power supply conductors, power supply voltage adaptation circuits and integrating analog to digital conversion circuits for each power supply domain or groups of power supply domains, and a common control input arranged to control start of integration in each of the integrating analog to digital conversion circuits collectively; and

a test control circuit arranged to cause control signals for independently selectable power supply voltage transitions to be sent to at least part of the power supply voltage adaptation circuits within a predetermined relative timing range with respect to the start of integration.

6. A test prepared integrated circuit with an internal power supply domain, the integrated circuit comprising;

an internal power supply conductor for said power supply domain; a power supply voltage adaptation circuit, for selectably adapting a power supply voltage on the internal power supply conductor; a test output;

an integrating analog to digital conversion circuit with an input coupled to the power supply conductor and an output coupled to the test output; and

an externally accessible terminal coupled to a control input of the integrating analog to digital conversion circuit, for supplying a duration signal that controls a duration of an integration time interval of the integrating analog to digital conversion circuit.

7. A test prepared integrated circuit with an internal power supply domain, the integrated circuit comprising;

an internal power supply conductor for said power supply domain; a power supply voltage adaptation circuit, for selectably adapting a power supply voltage on the internal power supply conductor;

a test output; an integrating analog to digital conversion circuit with an input coupled to the power supply conductor and an output coupled to the test output; and

a test control circuit with an internal timing circuit arranged to generate a duration signal and coupled to a control input of the integrating analog to digital conversion circuit, for supplying the duration signal to controls a duration of an integration time interval of the integrating analog to digital conversion circuit.

8. A test prepared integrated circuit with an internal power supply domain, the integrated circuit comprising;

an internal power supply conductor for said power supply domain; a power supply voltage adaptation circuit, for selectably adapting a power supply voltage on the internal power supply conductor;

a test output; an integrating analog to digital conversion circuit with an input coupled to the power supply conductor and an output coupled to the test output; and

a test control circuit having an input for receiving test commands, and outputs coupled to the integrating analog to digital conversion circuit and the power supply voltage adaptation circuit, the test control circuit being arranged to cause the integrating analog to digital conversion circuit to start integration and to cause the power supply voltage adaptation circuit to make a change in the power supply voltage with a relative timing within a predetermined range with respect to the start of integration in response to a test command.

9. A test prepared integrated circuit with an internal power supply domain, the integrated circuit comprising;

an internal power supply conductor for said power supply domain; a power supply voltage adaptation circuit, for selectably adapting a power supply voltage on the internal power supply conductor;

a test output; an integrating analog to digital conversion circuit with an input coupled to the power supply conductor and an output coupled to the test output; and

a reference value generator circuit and a comparator circuit, the comparator circuit having inputs coupled to the output of the integrating analog to digital conversion circuit and an output of the reference value generator circuit, the comparator circuit having an output coupled to the test output.

10. A method of testing an integrated circuit that comprises an internal power supply domain with a power supply voltage adaptation circuit to adapt the power supply voltage in the power supply domain, the method comprising of; applying the power supply voltage to an integrating analog to digital conversion circuit in the integrating circuit; measuring an integrated value of the power supply voltage, by maintaining a selected supply voltage during a measurement period, and reading an output signal established by the integrating analog to digital conversion circuit by temporal integration in the integrated circuit during the measurement period.

11. A method of testing an integrated circuit that comprises an internal power supply domain with a power supply voltage adaptation circuit to adapt the power supply voltage in the power supply domain, the method comprising of; applying the power supply voltage to an integrating analog to digital conversion circuit in the integrating circuit; measuring an integrated value of the power supply voltage, by maintaining a selected supply voltage during a measurement period, and reading an output signal established by the integrating analog to digital conversion circuit by temporal integration in the integrated circuit during the measurement period; and

measuring information about a supply voltage transition time, by sending control signals to the power supply voltage adaptation circuit to change over between mutually different supply voltages during a further measurement period and reading a further output signal established by the integrating analog to digital conversion circuit by temporal integration in the integrated circuit during the second measurement period.

12. A method of testing an integrated circuit that comprises an internal power supply domain with a power supply voltage adaptation circuit to adapt the power supply voltage in the power supply domain, the method comprising of; applying the power supply voltage to an integrating analog to digital conversion circuit in the integrating circuit; measuring an integrated value of the power supply voltage, by maintaining a selected supply voltage during a measurement period, and reading an output signal established by the integrating analog to digital conversion circuit by temporal integration in the integrated circuit during the measurement period; and

measuring an integrated value of the power supply voltages of a plurality of respective power supply voltage domains, by maintaining selected supply voltages in the respective power supply domains during the measurement period, and reading an output signal established by respective integrating analog to digital conversion circuits that temporally integrated the power supply voltages of respective ones of the power supply domains in the integrated circuit during the measurement period.

13. A method of testing an integrated circuit that comprises an internal power supply domain with a power supply voltage adaptation circuit to adapt the power supply voltage in the power supply domain, the method comprising of; applying the power supply voltage to an integrating analog to digital conversion circuit in the integrating circuit; measuring an integrated value of the power supply voltage, by maintaining a selected supply voltage during a measurement period, and reading an output signal established by the integrating analog to digital conversion circuit by temporal integration in the integrated circuit during the measurement period; and, wherein the integrated circuit comprises logic circuits with power supply connections coupled to the power supply voltage adaptation circuit, the method comprising measuring an activity dependence of the supply voltage, by sending a control signal to the power supply voltage adaptation circuit to maintain a selected supply voltage during the measurement period, and further control signals to the logic circuits to cause a selected activity in the logic circuits during the measurement period.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2015
From: NXP B.V.
To: III HOLDINGS 6, LLC
Reel/Frame 036304/0330 →
NUNC PRO TUNC ASSIGNMENT Recorded Aug 27, 2013
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 031093/0722 →
NUNC PRO TUNC ASSIGNMENT Recorded Aug 23, 2013
From: GOEL, SANDEEP KUMAR
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 031077/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2013
From: MEIJER, RINZE I. M. P.; PINEDA DE GYVEZ, JOSE DE JESUS
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 031074/0135 →