Method of fabricating a bipolar transistor
View Patent ↗A method of fabricating a bipolar transistor in a first trench ( 11 ) is disclosed wherein only one photolithographic mask is applied which forms a first trench ( 11 ) and a second trench ( 12 ). A collector region ( 21 ) is formed self-aligned in the first trench ( 11 ) and the second trench ( 12 ). A base region ( 31 ) is formed self-aligned on a portion of the collector region ( 21 ), which is in the first trench ( 11 ). An emitter region ( 41 ) is formed self-aligned on a portion of the base region ( 31 ). A contact to the collector region ( 21 ) is formed in the second trench ( 12 ) and a contact to the base region ( 31 ) is formed in the first trench ( 11 ). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.
1. A method for fabricating a bipolar transistor, the method comprising: providing a stack of layers on a semiconductor substrate, the stack of layers comprising a first isolation layer on the semiconductor substrate, a first semiconductor layer on the first isolation layer, a second isolation layer on the first semiconductor layer, and a second semiconductor layer on the second isolation layer, forming a first trench and a second trench in the stack of layers and in a portion of the semiconductor substrate, wherein the first trench and the second trench are separated by a protrusion which comprises a portion of the stack of layers and a first portion of the semiconductor substrate, removing the first portion of the semiconductor substrate, thereby creating an underpass region between the first trench and the second trench, in which the underpass region exposes a portion of the semiconductor substrate, forming a collector region on the exposed portions of the semiconductor substrate and a sealing region on the exposed portions of the first semiconductor layer and the second semiconductor layer, both regions comprising a semiconductor material, wherein the collector region fills the underpass region and the sealing region seals the second trench, forming a base region extending over a portion of the collector region in the first trench, forming spacers in the first trench, thereby forming an exposed portion of the collector region in the first trench, and forming an emitter region on the exposed portion of the collector region in the first trench.
2. The method as claimed in claim 1 , further comprising the steps of: removing the sealing region, and forming a collector contact on an exposed portion of the collector region in the second trench.
3. The method as claimed in claim 2 , further comprising the steps of: forming a base contact on a portion of the base region, which is in the first trench extending over the collector region.
4. The method as claimed in claim 2 , in which the base region also extends over the protrusion and further comprising the steps of: forming a base contact on a portion of the base region, which is on the protrusion.
5. The method as claimed in claim 1 , in which the semiconductor substrate, the first isolation layer and the first semiconductor layer are comprised in a Silicon-On-Insulator substrate.
6. The method as claimed in claim 1 , in which the method is integrated in a CMOS fabrication process wherein a CMOS device is formed which comprises a gate dielectric, which comprises the second isolation layer, and a gate electrode, which comprises the second semiconductor layer.