IP Library Patent Application 11914626
Patent Application
App. No. 11/914,626

Memory Management in a Computing Device

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Quick Facts
Patent No.
US None
App. No.
11/914,626
Abstract

A computing device incorporating memory such as mobile SDRAM, which is capable of conserving energy by being operated in a low-power self-refresh mode, is enabled to identify those regions of memory which are allocated but inactive. These regions are collected into specific banks of memory so as to create banks of memory containing only inactive data and which can then be placed in self-refresh. This reduces the power consumed by the computing device, and improves the energy efficiency of the device.

Claims (19)

1 . A method of managing resources in a computing device including memory capable of operating in a reduced functionality low-power mode, the method comprising

a. identifying blocks of memory which have been allocated but which are not in active use;

b. collecting the contents of the said inactive memory blocks in one or more physical memory banks identified for the collection of inactive data;

c. remapping the locations of the said inactive memory blocks to the said physical memory banks;

d. placing the said physical memory banks in a low-power mode for conserving energy; and wherein

e. subsequent access to any physical memory bank which has been placed in low-power mode causes the device to place the said physical memory bank into normal full-power operational mode.

2 . A method according to claim 1 wherein the memory is SDRAM, and in which the low power mode is self-refresh.

3 . A method according to claim 1 wherein the identification of those blocks of memory which are not in active use is managed via the maintenance of a most recently used list.

4 . A method according to claim 1 wherein an analysis of past patterns of memory usage is used to determine whether or not a particular region of memory is regarded as inactive.

5 . A method according to claim 1 wherein the collection of the contents of the said inactive memory blocks in one or more physical memory banks is carried out either by the null thread or by a background task.

6 . A method according to claim 1 wherein the collection of inactive memory blocks is performed by iteratively swapping blocks between a bank having active blocks and the most inactive blocks and the bank having active blocks and the least inactive blocks.

7 . A method according to claim 1 wherein

a. permissions on any physical memory banks containing inactive data in low-power mode are set so as to cause a processor exception when any of the said banks are accessed; and

b. a handler for the said processor exception switches the bank into normal operational mode and resets the permissions to stop further accesses generating an exception before the memory is re-accessed.

8 . A method according to claim 1 wherein a memory management unit (MMU) is used to facilitate the identification of when particular blocks of memory are accessed.

9 . A method according to claim 1 in wherein an MMU is used to remap the logical addresses of any memory blocks moved from one physical bank of memory to another.

10 . A method according to claim 1 wherein an access to one or more blocks of memory in a memory bank containing inactive data in low-power mode causes the said blocks of memory to be moved into an active memory bank, with the said one or more blocks of memory in the memory bank containing inactive data being placed again in low-power mode.

11 . A computing device programmed to implement a method according to claim 1 .

12 . An operating system for causing a computing device to operate in accordance with a method according to claim 1 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2009
From: SYMBIAN LIMITED; SYMBIAN SOFTWARE LIMITED
To: NOKIA CORPORATION
Reel/Frame 022240/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2008
From: FITZGERALD, RICHARD
To: SYMBIAN SOFTWARE LIMITED
Reel/Frame 020594/0229 →