Granted Patent B2

US 7,859,076 · App. 11/914,648 · Granted Dec 28, 2010

Abstract

Claims (17)

1. A semiconductor device with an edge termination structure, comprising:

a semiconductor body with opposed first and second major surfaces;

an active region of the semiconductor body defining at least one semiconductor component;

an edge termination region outside the active region, wherein the edge termination region includes:

a plurality of laterally spaced floating field regions;

an insulating layer over the first major surface; and

a plurality of field plates each electrically coupled at respective contact holes through the insulating layer to the first major surface in the edge termination region and extending inwards from the respective contact holes towards the active region over the plurality of floating field region, the plurality of field plates spaced from the active region defining at least one gap between adjacent field plates; such that the at least one gap between adjacent field plates is arranged over a joining region being a floating field region of greater width than the other floating field regions.

2. A semiconductor device according to claim 1 wherein: the floating field regions are semiconductor regions of first conductivity type at the first major surface; an underlying region of the semiconductor body of second conductivity type opposite to the first conductivity type underlies the floating field regions, the underlying region being spaced from the floating field regions by a spacer region of lower doping than the underlying region and the floating field regions.

3. A semiconductor device according to claim 2 wherein the spacer region of lower doping extends from the edge termination region into the active region and acts as the drift region in the active region.

4. A semiconductor device according to claim 2 wherein the spacer region includes regions of first conductivity type alternating with the regions of second conductivity type, the alternating regions of first and second conductivity type both being of lower doping than the floating field regions and the underlying region.

5. A semiconductor device according to claim 4 wherein the spacer region includes pillars including regions of first conductivity type vertically extending through the spacer region to the underlying region defining regions of second conductivity type between the pillars.

6. A semiconductor device according to claim 5 wherein in the edge termination region the pillars are arranged under the floating field regions.

7. A semiconductor device according to claim 4 wherein the spacer region includes laterally extending regions of first conductivity type alternating vertically with laterally extending regions of second conductivity type.

8. A semiconductor device according to claim 4 wherein the spacer region includes a plurality of regions of first conductivity type alternating with regions of second conductivity type both laterally and vertically.

9. A semiconductor device according to claim 2 wherein the floating field regions are arranged as a two dimensional array of regions at the first major surface in the edge termination region.

10. A semiconductor device according to claim 9 wherein the floating field regions are arranged as a hexagonal array of regions at the first major surface in the edge termination region.

11. A semiconductor device according to claim 1 wherein the spacing between adjacent floating field regions is greater in the edge region at greater distances from the active region than closer to the active region.

Assignments (16)