Semiconductor device
View Patent ↗At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
1. A semiconductor device comprising:
a memory-cell array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction crossing the plurality of word lines, and a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
a plurality of word driver circuits connected to the plurality of word lines;
a plurality of read circuits and a plurality of write circuits connected to the plurality of bit lines; and
a pulse-generating circuit comprising a plurality of NMOS transistors and a plurality of depletion MOS transistors configured to output a pulse based on a temperature characteristic,
wherein each of the plurality of memory cells includes
a first node connected to a corresponding one of the plurality of word lines;
a second node connected to a corresponding one of the plurality of bit lines;
a third node provided correspondingly to the second node;
a memory element in which a crystalline state is formed by a set operation and an amorphous state is formed by a reset operation; and
a switch element in which a current path from the second node to the third node via the memory element is formed upon reception of control of the first node,
wherein, at the time of the set operation, a first pulse is first input to the memory element and subsequently a second pulse is input, and
wherein a magnitude of the second pulse is changed by the pulse-generating circuit depending on an external temperature.
2. The semiconductor device according to claim 1 ,
wherein, at the time of the reset operation, a third pulse is input, and
wherein the third pulse has a constant magnitude independent of the external temperature.
3. The semiconductor device according to claim 1 ,
wherein the first and second pulses are voltage pulses, and
wherein the second pulse has a voltage value that is smaller than a voltage value of the first pulse and is decreased as the external temperature is increased.
4. The semiconductor device according to claim 1 ,
wherein the first and second pulses are current pulses, and
wherein the second pulse has a current value that is smaller than a current value of the first pulse and is decreased as the external temperature is increased.
5. The semiconductor device according to claim 2 ,
wherein the first pulse and the third pulse are identical to each other.
6. The semiconductor device according to claim 3 further comprising:
a power-supply circuit that generates a voltage value of the second pulse, and
wherein the power-supply circuit generates a temperature-dependent voltage value by using a temperature characteristic of a MOS transistor.
7. The semiconductor device according to claim 6 ,
wherein the power-supply circuit includes:
a circuit that generates a temperature-dependent current by using a temperature characteristic of an off current of a MOS transistor; and
a circuit that supplies the generated current to MOS transistors of two types different in a gradient of a characteristic of drain current/gate voltage and extracts a difference of gate voltages appearing between respective MOS transistors.
8. The semiconductor device according to claim 6 ,
wherein the power-supply circuit is arranged at a position having a relatively low temperature among positions adjacent to the memory-cell array.