Memory controller and method for coupling a network and a memory
View Patent ↗A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).
1. A memory controller for coupling a memory to a network having a network interface, wherein the network interface comprises network interface buffers for implementing a flow control across the network, and wherein the memory comprises a Dynamic Random Access Memory (DRAM) for being accessed in bursts via pre-fetch buffers and write-back buffers, the memory controller comprising:
a buffer managing unit for managing a buffering of data for the exchange of data between the network and the memory in bursts, the buffer managing unit further comprising:
a data control unit for monitoring the network interface buffers to determine whether sufficient data are present in the network interface buffers such that a burst of data can be written to the memory; and
a space control unit for monitoring whether sufficient space is available in the network interface buffers such that a burst of data from the memory can be buffered in the network interface buffers, wherein the data control unit and the space control unit control an access to and from the memory according to the data and the space in the network interface buffers and the pre-fetch buffers and the write-back buffers are entirely implemented in the network interface buffers.
2. The memory controller according to claim 1 , wherein the network interface is a Peripheral Component Interconnect (PCI) express interface.
3. The memory controller according to claim 2 , wherein network interface buffers are provided for a flow control virtual channel.
4. The memory controller according to claim 1 , wherein the buffer managing unit further comprises:
a space available counter that stores an amount of space in the network interface buffer;
a data available counter that stores an amount of data in the network interface buffer, wherein the buffer managing unit controls access to and from the memory according to the amount of space, the amount of data, and a burst size.
5. The memory controller according to claim 4 , wherein the buffer managing unit receives first information, when data is forwarded from the network interface to the network, and second information, when data is forwarded from the network interface to the memory, in order to update the space available counter and the data available counter.
6. A data processing system, comprising:
a network having at least one network interface for coupling a plurality of processing units;
a memory for storing data of the plurality of processing units; and
a memory controller according to claim 1 .
7. The memory controller of claim 1 , further comprising:
an input register coupled between the memory and the space control unit.
8. The memory controller of claim 7 , wherein the input register is coupled to an input of a transaction pending buffer.
9. The memory controller of claim 1 , further comprising:
an output register coupled between the memory and the data control unit.
10. The memory controller of claim 9 , wherein an output of a flow control buffer is coupled to the output register.
11. The memory controller of claim 1 , further comprising:
a burst size register coupled between the data control unit and the space control unit.
12. A method for coupling a memory to a network, wherein a flow control across the network is implemented by network interface buffers in a network interface of the network, wherein the memory comprises a Dynamic Random Access Memory (DRAM) for being accessed in bursts via pre-fetch buffers and write-back buffers, the method comprising:
managing a buffering of data for the exchange of data between the network and the memory in bursts by a buffer managing unit;
monitoring, with a data control unit, the network interface buffers to determine whether sufficient data are present in the network interface buffers such that a burst of data can be written to the memory;
monitoring, with a space control unit, whether sufficient space is available in the network interface buffers such that a burst of data from the memory can be buffered in the network interface buffers; and
controlling an access to and from the memory according to both the data and the space in the network interface buffers, wherein the pre-fetch buffers and the write-back buffers are entirely implemented in the network interface buffers.
13. The method of claim 12 , further comprising:
increasing a data available counter with each incoming data burst; and
decreasing the data available counter with each burst write by a burst size.
14. The method of claim 12 , further comprising:
filling a transaction pending buffer until space left inside the transaction pending buffer is smaller than a single burst size as monitored by a space available counter.
15. The method of claim 12 , further comprising:
resetting a size of a space available counter to a size of a transaction pending buffer.
16. The method of claim 12 , further comprising:
increasing a space available counter with each transmitted data burst; and
decreasing the space available counter with each burst read by a burst size.