Interconnection system
An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.
1. An interconnection network, comprising:
a motherboard having a top surface and a bottom surface and a plurality of circuit card connectors and having a plurality of groups of metallic traces, each group of metallic traces forming a point-to-point link electrically connecting a pair of circuit card connectors,
wherein each circuit card connector is fixedly attached to the top surface of the motherboard and has a first end and a second end joined by a first side and a second side and is adapted to accept a mating connector; and,
a group of the plurality of circuit card connectors oriented parallel to each other such that corresponding first ends and corresponding second ends of adjacent circuit card connectors are disposed proximal to each other,
wherein a physical connection location configuration of the point-to-point links with respect to circuit card connectors of the group of circuit card connectors of the plurality of connectors is selected from at least three of:
(a) first through third links being disposed such that all of the links connected to the circuit card connector lead away from a first side of the circuit card connector;
(b) first through third links being disposed such that the link of the links connected to the circuit card connector closest to the first end of the circuit card connector leads away from the first side of circuit card connector, and two links of the links lead away from the second side of the circuit card connector and the links leading away from the second side of the circuit card connector are disposed;
(c) the first through third links being disposed such that the link of the links connected to the circuit card connector closest to the second end of the circuit card connector leads away from the second side of the circuit card connector, the remaining links lead away from the first side of the circuit card connector and the links leading away from the first side of the circuit card connector are disposed adjacently;
(d) the first through third links being disposed such that the link of the links connecting to the circuit card connector closest to the first end of the circuit card connector and the link of the links connected to the circuit card connector closest to the second end of the circuit card connector lead away from the first side of the circuit card connector, and the link of the links disposed therebetween leads away from the second side of the circuit card connector;
and (e), (f), (g), and(h), wherein (e), (f), (g) and (h) are (a),(b), (c), and (d), wherein the first and second ends of the circuit card connector are interchanged by rotating a pattern of (a), (b), (c) and (d) by 180 degrees about an axis orthogonal to the circuit card connector,
wherein a network is formed by at least three circuit card connectors joined by the point-to-point links of the motherboard, at least three of the circuit card connectors of the network having a different physical connection location configuration selected from configurations (a) through (g),
wherein at least one circuit card connector is configured to accept a plug-in module comprising a configurable switching element (CSE), the configurable switching element (CSE) configured to control the future time status of one or more of an input or an output interface, and exchange a logical and a physical interface data assignment for a signal so that a differential time delay between signals on a first output interface and a second output interface is altered when measured at a second interface of a second CSE.
2. The network of claim 1 , wherein the circuit card connectors and the links connecting the circuit card connectors of the motherboard are passive elements.
3. The interconnection network of claim 1 , wherein the motherboard is configured such that modules plugged into connectors form a branching tree encompassing at least 7 connectors.
4. A method of laying out a network interconnection on a motherboard, the method comprising:
a top surface of a motherboard having a plurality of connectors oriented such that, when viewed from a top, first ends of adjacent connectors are positioned proximal to each other and seconds end of adjacent connectors are disposed proximal to each other and a connection interface of each connector of the motherboard is configured to connect to at least one of a first bi-directional point-to-point link, a second bidirectional point-to-point link or a third bi-directional point-to-point link,
wherein the first, the second and the third bi-directional point-to-point link links are each comprised of a group of printed circuit traces of the motherboard connecting a pair of connectors of the plurality of connectors; and
each connector of the motherboard has a physical connection location configuration and, where the network uses connectors having three different physical connection location configurations selected from:
(a) the first through third links of the motherboard being disposed such that all of the links lead away from a first side of the connector;
(b) the first through third links being disposed such that a link having a line closest to the first end leads away from the first side of the connector of the motherboard, and the remaining links lead away from the second side of the connector and the links leading away from the second side of the connector are disposed adjacently;
(c) the first through third links being disposed such that the link having closest to the second end leads away from the second side of the connector of the motherboard, and remaining links lead away from the first side of the connector and the links leading away from the first side of the connector are disposed adjacently;
(d) the first through third links being disposed such that the link closest to the first end and the link closest to the second end lead away from the first side of the connector, and the link disposed intermediate between the first and second links leads away from the second side of the connector; and
(e), (f), (g), and(h) wherein (e), (f), (g) and (h) are (a),(b), (c), and (d), wherein the top and bottom ends are interchanged by rotating a pattern of (a), (b), (c) and (d) by 180 degrees about an axis parallel to a length of the connectors,
wherein at least one connector is configured to accept a plug-in module comprising a configurable switching element (CSE), the configurable switching element (CSE) configured to control the future time status of one or more of an input or an output interface, and exchange a logical and a physical interface data assignment for a signal so that a differential time delay between signals on a first output interface and a second output interface is altered when measured at a second interface of a second CSE.
5. An interconnection network, comprising:
a plurality of memory modules; and
a motherboard having a plurality of connectors, each of the plurality of connectors interfacing with one of the plurality of memory modules,
wherein at least one of the plurality of connectors is configured to accept a plug-in module comprising a configurable switching element (CSE), the configurable switching element (CSE) configured to control the future time status of one or more of an input or an output interface, and exchange a logical and a physical interface data assignment for a signal so that a differential time delay between signals on a first output interface and a second output interface is altered when measured at a second interface of a second CSE.