Arrangement of MOSFET's for controlling same
View Patent ↗An arrangement of a plurality of MOSFET's on a chip that includes a first terminal, a second terminal and a third terminal is provided, the arrangement having at least one first MOSFET used as a first control cell and at least one second MOSFET used as a second control cell, each MOSFET having respectively a gate terminal, a source terminal and a drain terminal. The source terminals of all the MOSFET's are connected to one another and contacting the first terminal of the chip. The drain terminal of the at least one second MOSFET, which is used as a power cell, contacts the second terminal of the chip. The gate terminals of all the MOSFET's are connected to one another and contact the third terminal of the chip. The gate terminal and the drain terminal of the at least one first MOSFET, which is used as the first control cell, are connected to one another.
1. A MOSFET arrangement, comprising:
at least two MOSFETs provided on a chip, wherein the chip includes a first terminal, a second terminal and a third terminal, wherein at least one first MOSFET is used as a control cell and at least one second MOSFET is used as a power cell, and wherein the at least one first MOSFET and the at least one second MOSFET each have a gate terminal, a source terminal and a drain terminal;
wherein the source terminals of the at least one first MOSFET and the at least one second MOSFET are connected to one another and contact the first terminal of the chip;
wherein the drain terminal of the at least one second MOSFET contacts the second terminal of the chip;
wherein the gate terminals of the at least one first MOSFET and the at least one second MOSFET are connected to one another and directly contact the third terminal of the chip; and
wherein the gate terminal and the drain terminal of the at least one first MOSFET are connected to each other.
2. The arrangement as recited in claim 1 , wherein the gate terminal and the drain terminal of the at least one first MOSFET are connected to each other by at least one metallic connection having an intermediate insulator.
3. The arrangement as recited in claim 1 , wherein the at least one first MOSFET and the at least one second MOSFET are normally-off MOSFETs.
4. The arrangement as recited in claim 1 , wherein at least two first MOSFETs are provided, and wherein the at least two first MOSFETs are connected in parallel to form the control cell.
5. The arrangement as recited in claim 1 , wherein at least two second MOSFETs are provided, and wherein the at least two second MOSFETs are connected in parallel to form the power cell.
6. The arrangement as recited in claim 1 , wherein the at least one first MOSFET and the at least one second MOSFET are vertical MOSFETS.