CMOS process for fabrication of ultra small or non standard size or shape semiconductor die
View Patent ↗A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.
1. A method for the singulation of integrated circuit die, said method comprising:
Etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of said die;
Depositing a silicon nitride layer in said trench;
Coating said semiconductor layer with an oxide layer such that said trench is filled;
Removing part of said oxide layer from said semiconductor layer such that said oxide layer only remains in said trench;
Mounting said semiconductor layer with said oxide layer remaining only in said trench to a carrier;
Removing said silicon oxide dielectric layer, said nitride layer, and said oxide layer from said semiconductor layer mounted to said carrier; and
Releasing said die from said carrier.
2. The method according to claim 1 wherein said semiconductor layer comprises a complementary metal-oxide semiconductor circuit.
3. The method according to claim 1 wherein said oxide layer' comprises silicon oxide.
4. The method according to claim 1 wherein said removing said silicon oxide dielectric layer, said nitride layer, and said oxide layer comprises:
Selective wet etching of said silicon nitride layer; etching said oxide layer.
5. The method according to claim 4 wherein said etching said oxide layer comprises etching by a technique of etching selected from the group of techniques consisting of wet etching and plasma etching.
6. The method according to claim 1 wherein a plurality of trenches is formed in said substrate.
7. The method according to claim 1 further comprising bonding a second circuit to said semiconductor layer.
8. The method according to claim 7 wherein said bonding comprises: applying metallic pads to said semiconductor layer; coupling said metallic pads to said second circuit.
9. The method according to claim 1 wherein said releasing of said dies from said carrier comprises a solvent release.
10. The method according to claim 1 wherein said trench is non-linear.
11. The method according to claim 1 wherein said die is of a non-standard shape.
12. A method for the manufacture of a semiconductor die, said method comprising:
Fabricating a first semiconductor device on a wafer, said wafer being disposed on a silicon oxide dielectric layer;
Etching said wafer, thereby forming a trench defining a boundary of said die;
Depositing a silicon nitride layer in said trench;
Coating said semiconductor layer with an oxide layer such that said trench is filled;
Removing part of said oxide layer from said wafer such that said oxide layer remains only in said trench;
Mounting said wafer having only said trench filled with oxide layer to a carrier;
Removing said silicon oxide dielectric layer, said nitride layer, and said oxide layer from said wafer mounted to said carrier; and
Releasing said die from said carrier.
13. The method according to claim 12 , wherein said releasing said die from said carrier further comprises using solvents to release said die.
14. The method according to claim 12 wherein said step of removing said silicon oxide dielectric layer, said nitride layer, and said oxide layer, further comprises plasma etching said oxide layer.
15. The method according to claim 12 wherein said step of removing said silicon oxide dielectric layer, said nitride layer, and said oxide layer, further comprises wet etching said nitride layer.
16. The method according to claim 12 wherein said step of removing said silicon oxide dielectric layer, said nitride layer, and said oxide layer, further comprises back grinding and wet etching of said silicon oxide dielectric layer.
17. The method according to claim 12 wherein said carrier is of a carrier material selected from the group of fabric materials consisting of sapphire, silicon, anodized aluminum, and silicon carbide.
18. The method according to claim 12 wherein said trench is nonlinear.