Semiconductor memory device

1. A semiconductor memory device comprising a memory cell array provided with memory cells each having a variable resistance element capable of storing information when its electric resistance is changed by application of a voltage pulse, the memory cells being arranged in at least one direction of a row direction and column direction, the memory cell array being provided by connecting one end of each of the memory cells in the same row to a common word line and the other end of each of the memory cells in the same column to a common bit line, wherein

at least one of a voltage amplitude and a pulse width of a voltage pulse applied to an end of at least one of a selected word line connected to a selected memory cell among the word lines and a selected bit line connected to the selected memory cell among the bit lines is adjusted based on an arranged position of the selected memory cell in the memory cell array so that an electric resistance change of the variable resistance element after programming or erasing falls within a certain range regardless of the arranged position in the memory cell array according to an effective voltage amplitude or pulse width of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased among the memory cells in the memory cell array.

2. A semiconductor memory device comprising a memory cell array provided with memory cells each having a variable resistance element capable of storing information when its electric resistance is changed by application of a voltage pulse, the memory cells being arranged in at least one direction of a row direction and column direction, the memory cell array being provided by connecting one end of each of the memory cells in the same row to a common word line and the other end of each of the memory cells in the same column to a common bit line, wherein

a voltage amplitude of a voltage pulse applied to an end of at least one of a selected word line connected to a selected memory cell among the word lines and a selected bit line connected to the selected memory cell among the bit lines is adjusted based on an arranged position of the selected memory cell in the memory cell array so that an effective voltage amplitude of the voltage pulse applied to the variable resistance element of the selected memory cell to be programmed, erased or read among the memory cells in the memory cell array falls within a certain range regardless of the arranged position in the memory cell array.

3. The semiconductor memory device according to claim 1 , wherein

at least one of a voltage applied to ends of unselected word lines not connected to the selected memory cell among the word lines and a voltage applied to unselected bit lines not connected to the selected memory cell among the bit lines is adjusted based on the arranged position of the selected memory cell in the memory cell array during a memory action.

4. The semiconductor memory device according to claim 1 , wherein

when it is assumed that a voltage difference between ends of the selected word line and the selected bit line is V BW , the effective voltage amplitude applied to the variable resistance element of the selected memory cell is V R , an electric resistance value of the variable resistance element is R, and a total of wiring resistance from the ends of the selected word line and the selected bit line to the selected memory cell is R LINE , the voltage difference V BW is adjusted so that the effective voltage amplitude V R given by a formula that V R =R/(R+R LINE )×V BW is kept constant.

5. The semiconductor memory device according to claim 4 , wherein

when it is assumed that a power supply voltage is V DD , and a constant common to all the memory cells in the memory cell array is X, the voltage difference V BW is adjusted in proportion to (R+R LINE ) so as to satisfy a formula that V BW =X×(R+R LINE )×V DD .

6. The semiconductor memory device according to claim 4 comprising a voltage adjustment circuit for adjusting a voltage amplitude of a voltage pulse applied to an end of at least one of the selected word line and the selected bit line, wherein

the voltage adjustment circuit includes a plurality of switching circuits whose number is not more than the total number of the memory cells in the memory cell array, and

the plurality of switching circuits are turned ON/OFF by a decode signal selecting at least one of the selected word line and the selected bit line.

7. The semiconductor memory device according to claim 5 comprising

a voltage adjustment circuit for adjusting a voltage amplitude of a voltage pulse applied to an end of at least one of the selected word line and the selected bit line, wherein

the voltage adjustment circuit includes an amplifier and a plurality of switching circuits whose number is not more than the total number of the memory cells in the memory cell array,

the plurality of switching circuits are turned ON/OFF by a decode signal selecting at least one of the selected word line and the selected bit line,

an output voltage V 1 of the switching circuit controlled to be in an ON state is adjusted so as to satisfy a formula that V 1 =Y×(R+R LINE )×V DD , where Y is a constant, and

the voltage difference V BW is provided by amplifying the output voltage V 1 by the amplifier.

8. A semiconductor memory device comprising a memory cell array provided with memory cells each having a variable resistance element capable of storing information when its electric resistance is changed by application of a voltage pulse, the memory cells being arranged in at least one direction of a row direction and column direction, the memory cell array being provided by connecting one end of each of the memory cells in the same row to a common word line and the other end of each of the memory cells in the same column to a common bit line, wherein

a pulse width of a voltage pulse applied to an end of at least one of a selected word line connected to a selected memory cell among the word lines and a selected bit line connected to the selected memory cell among the bit lines is adjusted based on an arranged position of the selected memory cell in the memory cell array so that an electric resistance change of the variable resistance element after programming or erasing falls within a certain range regardless of the arranged position in the memory cell array according to an effective pulse width of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased among the memory cells in the memory cell array.

9. The semiconductor memory device according to claim 8 , wherein

the pulse width is adjusted by the number of voltage pulses discretely applied to an end of at least one of the selected word line and the selected bit line.

10. The semiconductor memory device according to claim 1 , wherein

the memory cell array is provided with the memory cells arranged in a row direction and a column direction, and by connecting one end of the variable resistance element as one terminal of each of the memory cells in the same row to the common word line, and the other end of the variable resistance element as the other terminal of each of the memory cells in the same column to the common bit line.

11. The semiconductor memory device according to claim 2 , wherein

at least one of a voltage applied to ends of unselected word lines not connected to the selected memory cell among the word lines and a voltage applied to unselected bit lines not connected to the selected memory cell among the bit lines is adjusted based on the arranged position of the selected memory cell in the memory cell array during a memory action.

12. The semiconductor memory device according to claim 2 , wherein

when it is assumed that a voltage difference between ends of the selected word line and the selected bit line is VBW, the effective voltage amplitude applied to the variable resistance element of the selected memory cell is VR, an electric resistance value of the variable resistance element is R, and a total of wiring resistance from the ends of the selected word line and the selected bit line to the selected memory cell is RLINE, the voltage difference VBW is adjusted so that the effective voltage amplitude VR given by a formula that VR=R/(R+RLINE)×VBW is kept constant.

13. The semiconductor memory device according to claim 12 , wherein

when it is assumed that a power supply voltage is VDD, and a constant common to all the memory cells in the memory cell array is X, the voltage difference VBW is adjusted in proportion to (R+RLINE) so as to satisfy a formula that VBW=X×(R RLINE)×VDD.

14. The semiconductor memory device according to claim 12 comprising

a voltage adjustment circuit for adjusting a voltage amplitude of a voltage pulse applied to an end of at least one of the selected word line and the selected bit line, wherein

the voltage adjustment circuit includes a plurality of switching circuits whose number is not more than the total number of the memory cells in the memory cell array, and

the plurality of switching circuits are turned ON/OFF by a decode signal selecting at least one of the selected word line and the selected bit line.

15. The semiconductor memory device according to claim 13 comprising

a voltage adjustment circuit for adjusting a voltage amplitude of a voltage pulse applied to an end of at least one of the selected word line and the selected bit line, wherein

the voltage adjustment circuit includes an amplifier and a plurality of switching circuits whose number is not more than the total number of the memory cells in the memory cell array,

the plurality of switching circuits are turned ON/OFF by a decode signal selecting at least one of the selected word line and the selected bit line,

an output voltage V 1 of the switching circuit controlled to be in an ON state is adjusted so as to satisfy a formula that V 1 =Y×R+RLINE)×VDD, where Y is a constant, and

the voltage difference VBW is provided by amplifying the output voltage V 1 by the amplifier.

16. The semiconductor memory device according to claim 2 , wherein

the memory cell array is provided with the memory cells arranged in a row direction and a column direction, and by connecting one end of the variable resistance element as one terminal of each of the memory cells in the same row to the common word line, and the other end of the variable resistance element as the other terminal of each of the memory cells in the same column to the common bit line.

17. The semiconductor memory device according to claim 8 , wherein

the memory cell array is provided with the memory cells arranged in a row direction and a column direction, and by connecting one end of the variable resistance element as one terminal of each of the memory cells in the same row to the common word line, and the other end of the variable resistance element as the other terminal of each of the memory cells in the same column to the common bit line.