Incremental state updates
View Patent ↗A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple threads require access to sets of state information which differ from one another by a relatively small number of state changes.
1. A method for managing incremental state updates to data in a processor, the processor including a register and a memory, the register configured to store entries, each entry including a data value, an address corresponding to a memory address, and a data time stamp, the processor configured to execute one or more threads, each thread having a thread time stamp, the method comprising:
checking the register for an entry corresponding to a memory address;
if there is no entry in the register corresponding to the memory address, then retrieving a data value from the memory address;
if there is an entry in the register corresponding to the memory address, retrieving a data value from the entry in the register corresponding to the memory address only if the data time stamp of the data value is earlier than the thread time stamp; and
executing the thread with the retrieved data value.
2. The method according to claim 1 , further comprising:
storing updates to data in the register, each update to data including a data value, an address corresponding to a memory address, and a data time stamp corresponding to a time when the update to data is stored.
3. The method according to claim 2 , further comprising:
if the register is full, sending a stall signal to prevent the register from being overwritten by new entries until all earlier time stamped threads complete execution.
4. A processor for managing incremental state updates to data, comprising:
a memory; and
a register in communication with the memory, the register configured to store entries, each entry including a data value, an address corresponding to a memory address, and a data time stamp;
wherein the processor is configured to:
check the register for an entry corresponding to a memory address;
if there is no entry in the register corresponding to the memory address, then retrieve a data value from the memory address;
if there is an entry in the register corresponding to the memory address, retrieve a data value from the entry in the register corresponding to the memory address only if the data time stamp of the data value is earlier than a thread time stamp; and
execute the thread with the retrieved data value.
5. The processor according to claim 4 , wherein the processor is further configured to:
store updates to data in the register, each update to data including a data value, an address corresponding to a memory address, and a data time stamp corresponding to a time when the update to data is stored.
6. The processor according to claim 5 , wherein if the register is full, the processor is further configured to:
send a stall signal to prevent the register from being overwritten by new entries until all earlier time stamped threads complete execution.
7. The processor according to claim 4 , further comprising:
a time stamp manager in communication with the register, the time stamp manager configured to keep track of which thread time stamp is an oldest and which thread time stamp is a newest.
8. A processor for managing incremental state updates to data, comprising:
a constant file, including a memory and a register in communication with the memory, the register configured to store entries, each entry including a data value, an address corresponding to a memory address, and a data time stamp;
a command processor in communication with the constant file, the command processor configured to update data in the constant file by storing updates to data in the register, each update to data including a data value, an address corresponding to a memory address, and a data time stamp corresponding to a time when the update to data is stored; and
a programmable processor in communication with the constant file and the command processor, the programmable processor configured to:
check the register for an entry corresponding to a memory address;
if there is no entry in the register corresponding to the memory address, then retrieve a data value from the memory address;
if there is an entry in the register corresponding to the memory address, retrieve a data value from the entry in the register corresponding to the memory address only if the data time stamp of the data value is earlier than a thread time stamp; and
execute the thread with the retrieved data value.
9. The processor according to claim 8 , wherein:
the command processor is further configured to send a command to the programmable processor; and
the programmable processor is further configured to create one or more threads to execute the command.
10. The processor according to claim 8 , wherein if the register is full, the constant file is configured to send a stall command to the command processor such that the command processor stalls all newer threads from executing until all earlier time stamped threads complete executing.
11. The processor according to claim 10 , wherein the programmable processor is further configured to send a completion signal to the constant file when all of the threads having a same thread time stamp have completed executing.
12. The processor according to claim 8 , wherein the constant file further includes a time stamp manager in communication with the register, the time stamp manager configured to keep track of which thread time stamp is an oldest and which thread time stamp is a newest.
13. A computer-readable storage medium storing a set of instructions for execution by one or more processors to facilitate manufacture of a processor for managing incremental state updates to data, the processor comprising:
a constant file, including a memory and a register in communication with the memory, the register configured to store entries, each entry including a data value, an address corresponding to a memory address, and a data time stamp;
a command processor in communication with the constant file, the command processor configured to update data in the constant file by storing updates to data in the register, each update to data including a data value, an address corresponding to a memory address, and a data time stamp corresponding to a time when the update to data is stored; and
a programmable processor in communication with the constant file and the command processor, the programmable processor configured to:
check the register for an entry corresponding to a memory address;
if there is no entry in the register corresponding to the memory address, then retrieve a data value from the memory address;
if there is an entry in the register corresponding to the memory address, retrieve a data value from the entry in the register corresponding to the memory address only if the data time stamp of the data value is earlier than a thread time stamp; and
execute the thread with the retrieved data value.
14. The computer-readable storage medium of claim 13 , wherein the instructions are hardware description language (HDL) instructions used for the manufacture of a device.