Energy capture circuit
View Patent ↗An energy capture circuit for capturing energy in response to an input pulse. The circuit is constructed and arranged to transfer input energy in time divided portions among subcircuits. This includes a storage means, a clock means, at least two subcircuits, and at least one transfer circuit. Each subcircuit includes a first inductive means in operative communication with the input source, a rectifying means for producing a positive current in operative communication with the first inductive means, a capacitive means in operative communication with the rectifying means, and a switch means in operative communication with the capacitive means. At least one transfer circuit is in operative communication with each of the switch means of the at least two subcircuits. The output of the clock means is in operative communication with both a first switch means and an inverter means, the inverter means having an output in operative communication with a second switch means.
1. A high efficiency energy capture circuit for capturing energy in response to an input pulse from an input source, the circuit comprising:
a storage means having a first and a second terminal;
a clock means having an output;
at least two subcircuits, each subcircuit comprising:
a first inductive means, the first inductive means comprising a first and a second terminal, the first terminal in operative communication with the input source;
a rectifying means for producing a positive current, the rectifying means comprising a first terminal and a second terminal, the first terminal in operative communication with the second terminal of the first inductive means;
a capacitive means comprising a first terminal and a second terminal, the first terminal of the capacitive means in operative communication with the second terminal of the rectifying means and the second terminal of the capacitive means in operative communication with a circuit ground;
a switch means comprising a first terminal and a second terminal, the first terminal in operative communication with the first terminal of the capacitive means; and
at least one transfer circuit being in operative communication with each of the switch means of the at least two subcircuits,
wherein the output of the clock means is in operative communication with a first switch means, the clock output further in operative communication with an inverter means, the inverter means having an output in operative communication with a second switch means.
2. The circuit arrangement of claim 1 , wherein the at least one transfer circuit comprises:
at least one current interruption means, the at least one current interruption means comprising a first terminal and a second terminal, the first terminal of least one current interruption means in operative communication with the second terminal of the switch means;
a second inductive means comprising a first and a second terminal, the first terminal of the second inductive means in operative communication with the second terminal of the current interruption means, the second terminal of the second inductive means in operative communication with the first terminal of the storage means.
3. The circuit arrangement of claim 1 , wherein the clock output in operative communication with the first switch means is out-of-phase with the inverter output in operative communication with the second switch means.
4. The circuit arrangement of claim 3 , wherein the clock output and the inverter output are 180 degrees out-of-phase with one another.
5. The circuit arrangement of claim 1 , wherein the rectifying means is a diode.
6. The circuit arrangement of claim 1 , wherein the first inductive means is an inductor.
7. The circuit arrangement of claim 1 , wherein the switch means further comprises a third terminal, the clock output being in operative communication with the third terminal.
8. The circuit arrangement of claim 7 , wherein the switch means is a transistor selected from the group consisting of bipolar junction transistors and field effect transistors.
9. The circuit arrangement of claim 1 , wherein the input current pulse is DC containing a 5% ripple with a period of about 50 microseconds.
10. The circuit arrangement of claim 1 , wherein the second inductive means is a filter inductor.
11. The circuit arrangement of claim 10 , further comprising a free wheeling diode having a first and a second terminal, the first terminal in operative communication with the first terminal of the filter inductor.
12. The circuit arrangement of claim 1 , wherein the first inductor means has a nominal value of about 20 mH.
13. The circuit arrangement of claim 1 , wherein the capacitive means is at least one capacitor.
14. The circuit arrangement of claim 13 , wherein the at least one capacitor has a value of about 27 nF.
15. The circuit arrangement of claim 1 , wherein the storage means is at least one capacitor.
16. A high efficiency energy capture circuit for capturing energy in response to an input pulse from an input source, the circuit comprising:
a storage capacitor having a first and a second terminal;
a clock having an output;
at least two subcircuits, each subcircuit comprising:
a first inductor, the first inductor comprising a first and a second terminal, the first terminal in operative communication with the input source;
a rectifying diode for producing a positive current, the rectifying diode comprising a first terminal and a second terminal, the first terminal in operative communication with the second terminal of the first inductor;
a capacitor comprising a first terminal and a second terminal, the first terminal of the capacitor in operative communication with the second terminal of the rectifying diode and the second terminal of the capacitor in operative communication with a circuit ground;
a transistor comprising a first terminal, a second terminal, and a third terminal, the first terminal in operative communication with the first terminal of the capacitor; and
at least one transfer circuit being in operative communication with the second terminal of each transistor of the at least two subcircuits,
wherein the output of the clock is in operative communication with the third terminal of a first transistor, the clock output further in operative communication with an inverter, the inverter having an output in operative communication with a second transistor.
17. A method of capturing energy in response to an input pulse from an input source, the method comprising:
providing a storage capacitor having a first and a second terminal;
providing a clock having an output;
providing at least two subcircuits, each subcircuit comprising:
a first inductor, the first inductor in operative communication with the input source;
a rectifying diode for producing a positive current, the rectifying diode comprising a first terminal and a second terminal, the first terminal in operative communication with the first inductor;
a capacitor comprising a first terminal and a second terminal, the first terminal of the capacitor in operative communication with the second terminal of the rectifying means and the second terminal of the capacitor in operative communication with a circuit ground;
a transistor comprising a first terminal, a second terminal, and a third terminal, the first terminal in operative communication with the first terminal of the capacitor;
providing at least one transfer circuit in operative communication with each of the at least two subcircuits;
applying a clock signal to the at least two circuits with a clock means, the clock means having an output in operative communication with a first transistor, the clock output further in operative communication with an inverter, the inverter having an output in operative communication with a second transistor; and
storing the energy in a storage capacitor, the storage capacitor having a first and second terminal, the first terminal being in operative communication with the at least one transfer circuit.