PFC and ballast control IC
View Patent ↗The IRS21681D is a fully integrated, fully protected 600V ballast control IC designed to drive all types of fluorescent lamps. The IRS21681D is based on the popular IR2166 control IC with additional improvements to increase ballast performance. PFC circuitry operates in critical conduction mode and provides high PF, low THD and DC bus regulation. The IRS21681D features include programmable preheat and run frequencies, programmable preheat time, programmable ignition ramp, programmable PFC over-current protection, and programmable end-of-life protection. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, DC bus under-voltage reset as well as an automatic restart function, have been included in the design. The IRS2168D has, in addition, closed-loop half-bridge ignition current regulation and a novel fault counter. The IRS21681D, unlike the IRS2168D, ramps up during ignition and shuts down at the first over-current fault. The IRS21681D and IRS2168D are both available in either 16-pin PDIP or 16-pin narrow body SOIC packages.
1. An IC for controlling a power supply circuit for delivering power to a load circuit including an output stage, comprising:
ballast control and driver circuitry that provides drive signals to the power supply circuit, receives current sense signals indicative of current in said output stage, and responds to the current sense signals by modifying the drive signals;
the ballast control and driver circuitry including:
drive circuitry that provides the drive signals; and
fault detection circuitry that receives the current sense signals and provides a detect signal in response to a fault in the output stage, and in response to said detect signal, causes the drive circuitry to cease providing the drive signals,
wherein said fault detection circuitry comprises an internal fault counter that delays termination of said drive signals until a predetermined number of consecutive detect signals have been counted; and
wherein said ballast control and driver circuitry is configured to discharge a DC bus voltage from said power supply circuit through an internal MOSFET down to a ballast power off (UVLO-) threshold and said drive signals are latched low when said IC is in a run mode and when said DC bus voltage decreases below 3.0V.
2. The IC of claim 1 , wherein each detect signal corresponds to an overcurrent condition coinciding with one of said drive signals.
3. The IC of claim 2 , wherein said internal fault counter counts down in each cycle when there is no fault and the overcurrent faults are not consecutive.
4. The IC of claim 1 , wherein said ballast control and driver circuitry has a plurality of operating modes including preheat, ignition and run modes;
wherein said drive circuitry comprises a variable frequency oscillator providing said drive signals, the operating frequency of the oscillator being responsive to a current at an FMIN pin of said IC; said FMIN pin being connected to a voltage source and to said oscillator;
in the run mode, said current being determined by said voltage source and a resistor RFMIN connected to said FMIN pin.
5. The IC of claim 4 , wherein said current is determined in the preheat mode by the parallel combination of the RFMIN resistor and a resistor RPH which is connected to the FMIN pin and to a pin VCO of said IC, said IC having an internal switch connected to the pin VCO which is open in run mode for disconnecting RPH but closed in preheat mode for connecting RPH in parallel with RFMIN.
6. The IC of claim 5 , further comprising a capacitor CVCO connected to the pin VCO and providing a variable voltage at the VCO pin for varying the frequency range between a maximum frequency in preheat mode to a minimum frequency in run mode.
7. The IC of claim 6 , wherein said output stage is a fluorescent lamp resonant output stage, and wherein said frequency range includes a resonance frequency for igniting the lamp.
8. The IC of claim 1 , wherein said ballast control and driver circuitry has a plurality of operating modes including preheat and ignition modes;
further comprising a timing capacitor and a circuit for charging said capacitor;
said ballast control and driver circuitry remaining in preheat mode until said timing capacitor is charged to a first predetermined voltage, then discharging said capacitor to a second predetermined voltage, then remaining in ignition mode until said capacitor again reaches said first predetermined voltage.
9. The IC of claim 8 , wherein said first and second predetermined voltages are respectively ⅔ and ⅓ of an IC supply voltage.
10. The IC of claim 8 , wherein said IC has an internal switching circuit for rapidly discharging said timing capacitor from said first to said second predetermined voltage.
11. The IC of claim 8 , wherein said timing capacitor and charging circuit are external of said IC.
12. The IC of claim 8 , wherein the duration of said preheat mode is approximately twice the duration of the ignition mode.
13. The IC of claim 1 , wherein said output stage is a fluorescent lamp resonant output stage.
14. The IC of claim 13 , wherein said ballast control and driver circuitry comprises an end-of-life (EOL) window comparator which receives a lamp voltage signal at an EOL pin and generates an EOL fault signal when said lamp voltage is greater or less than a predetermined range; and
further comprising a bias circuit connected to the EOL pin for biasing said lamp voltage signal at an intermediate level within said predetermined range.
15. The IC of claim 14 , wherein said bias circuit comprises an operational transconductance amplifier referenced to a reference voltage at said intermediate level.
16. The IC of claim 14 , wherein said predetermined range is about 1V to 3V and said intermediate level is about 2V.
17. A method of controlling a power supply circuit for delivering power to a load circuit including an output stage, comprising the steps of:
providing drive signals to the power supply circuit, receiving current sense signals indicative of current in said output stage, and responding to the current sense signals by modifying the drive signals;
receiving the current sense signals and providing a detect signal in response to a fault in the output stage, and in response to said detect signal, causing the drive circuitry to cease providing the drive signals, further comprising the steps of:
employing an internal fault counter to delay termination of said drive signals until a predetermined number of consecutive detect signals have been counted; and
discharging a DC bus voltage from said power supply circuit through an internal MOSFET down to a ballast power off (UVLO-) threshold and latching said drive signals low when in a run mode and when said DC bus voltage decreases below 3.0V.
18. The method of claim 17 , wherein each detect signal corresponds to an overcurrent condition coinciding with one of said drive signals.
19. The method of claim 18 , wherein said internal fault counter counts down in each cycle when there is no fault and the overcurrent faults are not consecutive.
20. The method of claim 17 wherein said output stage is a fluorescent lamp resonant output stage, further comprising:
receiving a lamp voltage signal at an end-of-life (EOL) window comparator and generating an EOL fault signal when said lamp voltage is greater or less than a predetermined range; and
biasing said lamp voltage signal at an intermediate level within said predetermined range.
21. The method of claim 20 , wherein said predetermined range is about 1V to 3V and said intermediate level is about 2V.