Radiation hardened logic circuits

1. A radiation hardened inverter comprising

first and second electrical paths between an input terminal and an output terminal,

a first PFET disposed in the first electrical path, and

a bipolar junction transistor (BJT) disposed in the second electrical path,

wherein the first PFET is configured to convert a low level signal at the input terminal to a high level signal at the output terminal,

the BJT is configured to convert a high level signal at the input terminal to a low level signal at the output terminal, and

a second PFET disposed in the second electrical path,

wherein the second PFET is configured to provide a path for bleeding excess current away from the BJT.

2. The radiation hardened inverter of claim 1 including

a current limiting PFET disposed in the second electrical path,

wherein the current limiting PEET is configured to limit current flowing into a base of the BJT.

3. The radiation hardened inverter of claim 2 wherein

the current limiting PFET includes a body, and

the body is connected to the input terminal.

4. The radiation hardened inverter of claim 1 wherein

the first PFET includes a gate connected to the input terminal, a source connected to a voltage reference, and a drain connected to the output terminal,

the second PFET includes a gate connected to a ground reference, a source connected to a base of the BJT, and a drain connected to the ground reference, and

the BJT includes a collector connected to the output terminal, and an emitter connected to the ground reference.

5. The radiation hardened inverter of claim 4 including

a current limiting PFET disposed in the second electrical path,

wherein the current limiting PFET includes a gate connected to the ground reference, a source connected to the input terminal, and a drain connected to the base of the BJT.

6. The radiation hardened inverter of claim 1 wherein

a capacitor is coupled between the second PFET and the input terminal for speeding up conversion of the low level signal at the input terminal to the high level signal at the output terminal.

7. The radiation hardened inverter of claim 1 wherein

each of the first and second PFETs includes a body, and

each body is connected to one voltage reference.

8. The radiation hardened inverter of claim 1 wherein the first and second paths are free-of an NFET.

9. The radiation hardened inverter of claim 1 wherein

the BJT is configured to reduce dosing effects due to one of ionizing radiation in outer space, residual radiation from isotopes in chip packaging material, or radiation from nuclear explosion.

10. A radiation hardened NAND gate comprising

first and second electrical paths between a first input terminal and an output terminal,

third and fourth electrical paths between a second input terminal and the output terminal,

a first PFET disposed in the first electrical path,

a first BJT disposed in the second electrical path,

a second PFET disposed in the third electrical path, and

a second BJT disposed in the fourth electrical path,

wherein the first and second PFETs convert a low level signal at the first or second input terminal to a high level signal at the output terminal,

the first and second BJTs convert high level signals, respectively, at the first and second input terminals to a low level signal at the output terminal

a third PFET disposed in the second electrical path, and

a fourth PFET disposed in the fourth electrical path,

wherein the third and fourth PFETs, respectively, bleed excess current away from the first and second BJTs.

11. The radiation hardened NAND gate of claim 10 including

first and second current limiting PFETs disposed, respectively, in the second and fourth electrical paths,

wherein the first and second current limiting PFETs are configured to limit current flowing into a respective base of the first and second BJTs.

12. The radiation hardened NAND gate of claim 11 wherein

the first and second current limiting PFETs include first and second bodies , and

the first body is connected to the first input terminal, and

the second body is connected to the second input terminal.

13. The radiation hardened NAND gate of claim 10 wherein

the first PFET includes a gate connected to the first input terminal, a source connected to a voltage reference, and a drain connected to the output terminal,

the third PFET includes a gate connected to a ground reference, a source connected to a base of the first BJT, and a drain connected to the ground reference,

the first BJT includes a collector connected to the output terminal, and an emitter connected to a collector of the second BJT,

the second PFET includes a gate connected to the second input terminal, a source connected to the voltage reference, and a drain connected to the output terminal,

the fourth PFET includes a gate connected to the ground reference, a source connected to a base of the second BJT, and a drain connected to the ground reference, and

the second BJT includes an emitter connected to the ground reference.

14. The radiation hardened NAND gate of claim 13 including

a first current limiting PFET disposed in the second electrical path,

wherein the first current limiting PEET includes a gate connected to the ground reference, a source connected to the first input terminal, and a drain connected to the base of the first BJT, and

a second current limiting PFET disposed in the fourth electrical path,

wherein the second current limiting PFET includes a gate connected to the ground reference, a source connected to the second input terminal, and a drain connected to the base of the second BJT.

15. The radiation hardened NAND gate of claim 10 wherein

a first capacitor is coupled between the third PFET and the first input terminal for speeding up conversion of the low level signal at the first input terminal to the high level signal at the output terminal, and

a second capacitor is coupled between the fourth PEET and the second input terminal for speeding up conversion of the low level signal at the second input terminal to the high level signal at the output terminal.

16. The radiation hardened NAND gate of claim 10 wherein

each of the first, second, third and fourth PFETs includes a body, and

each body is connected to one voltage reference.

17. The radiation hardened NAND gate of claim 10 wherein

the first, second, third and fourth electrical paths are free-of an NFET.

18. The radiation hardened NAND gate of claim 10 wherein

the first and second BJTs are configured to reduce dosing effects due to one of ionizing radiation in outer space, residual radiation from isotopes in chip packaging material, radiation from nuclear explosion.

19. The radiation hardened NAND gate of claim 10 wherein

the first and second BJTs are replacements for radiation susceptible NFETs, and provide radiation hardening.