FAST AUDIO AND ANGLE SWITCHING VIA MULTIPLE DEMUX BUFFERS
Presented herein are system(s) and method(s) for fast audio and angle switching via multiple demux buffers. In one embodiment, there is presented a circuit for decoding data. The circuit comprises a processor, a system clock, a plurality of queues, and at least one decoder. The processor demultiplexes a plurality of elementary streams from a multiplexed stream, wherein each of the plurality of elementary streams include portions, wherein each of the portions include time stamps. The system clock maintains a clock reference. The plurality of FIFOs correspond to the plurality of elementary streams and FIFO each of the plurality of elementary streams, wherein each of the plurality of FIFOs include a front end, and wherein the front end of each of the plurality of FIFOs stores the portion of the corresponding FIFO that includes a time stamp that is proximate to the clock reference. The at least one decoder decodes selected ones of the plurality of elementary streams by decoding portions at the front end of the FIFO corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of elementary streams by switching from decoding portions at the front end of a FIFO corresponding to one of the selected ones of the plurality of elementary streams to decoding portions at the front end of a FIFO corresponding to the newly selected one of the plurality of elementary streams.
1 . A circuit for decoding data, said circuit comprising:
a processor for demultiplexing a plurality of elementary streams from a multiplexed stream, wherein each of the plurality of elementary streams comprises portions, wherein each of the portions comprises time stamps;
a system clock for maintaining a clock reference;
a plurality of FIFOs corresponding to the plurality of elementary streams for queuing each of the plurality of elementary streams, wherein each of the plurality of FIFOs comprise a front end, and wherein the front end of each of the plurality of FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and
at least one decoder for decoding selected ones of the plurality of elementary streams by decoding portions at the front end of the FIFO corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of elementary streams by switching from decoding portions at the front end of a FIFO corresponding to one of the selected ones of the plurality of elementary streams to decoding portions at the front end of a FIFO corresponding to the newly selected one of the plurality of elementary streams.
2 . The circuit of claim 1 , wherein the at least one decoder further comprises:
an extractor for receiving the selected ones of the elementary stream; and
a decompression engine for decompressing selected ones of the elementary streams.
3 . The circuit of claim 1 , wherein plurality of elementary streams comprise audio elementary stream and a video elementary stream.
4 . The circuit of claim 1 , wherein the multiplexed stream comprises a transport stream.
5 . The circuit of claim 1 , wherein the multiplexed stream comprises a program stream.
6 . The circuit of claim 1 , wherein the at least one decoder further comprises:
a video decoder for decoding video data; and
an audio decoder for decoding audio data.
7 . An integrated circuit for decoding data, said integrated circuit comprising:
a transport processor for receiving a transport stream, said transport stream comprising a plurality of packets, each of the packets comprising a portion of one of a plurality video elementary streams and a plurality of audio elementary streams, an identifier identifying the one of the plurality video elementary streams and a plurality of audio elementary streams, and a time stamp, wherein said transport processor demultiplexes each of the plurality of video elementary streams and the plurality of audio elementary streams by demultiplexing the portions of the video elementary streams and the audio elementary streams;
a system clock for maintaining a clock reference;
a plurality of audio FIFOs corresponding to the plurality of audio elementary streams for queuing each of the plurality of audio elementary streams, wherein each of the plurality of audio FIFOs comprise a front end, and wherein the front end of each of the plurality of audio FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and
a plurality of video FIFOs corresponding to the plurality of video elementary streams for queuing each of the plurality of video elementary streams, wherein each of the plurality of video FIFOs comprise a front end, and wherein the front end of each of the plurality of video FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference.
8 . The integrated circuit of claim 7 , further comprising:
at least one audio decoder for decoding selected ones of the plurality of audio elementary streams by decoding portions at the front end of audio FIFOs corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of audio elementary streams by switching from decoding portions at the front end of an audio FIFO corresponding to one of the selected ones of the plurality of audio elementary streams to decoding portions at the front end of an audio FIFO corresponding to the newly selected one of the plurality of audio elementary streams.
9 . The integrated circuit of claim 8 , wherein the at least one video decoder further comprises:
an extractor for receiving the selected ones of the video elementary stream; and
a video decompression engine for decompressing selected ones of the video elementary streams.
10 . The integrated circuit of claim 7 , further comprising:
at least one video decoder for decoding selected ones of the plurality of video elementary streams by decoding portions at the front end of video FIFOs corresponding to the selected ones of the plurality of video elementary streams and a newly selected one of the plurality of video elementary streams by switching from decoding portions at the front end of an video FIFO corresponding to one of the selected ones of the plurality of video elementary streams to decoding portions at the front end of an video FIFO corresponding to the newly selected one of the plurality of video elementary streams.
11 . The integrated circuit of claim 10 , wherein the at least one video decoder further comprises:
an extractor for receiving the selected ones of the video elementary stream; and
a video decompression engine for decompressing selected ones of the elementary streams.
12 . A method for decoding data, said method comprising:
receiving a program stream, said program stream comprising a plurality of packs, each of the packs comprising a portion of one of a plurality video elementary streams and a plurality of audio elementary streams, an identifier identifying the one of the plurality video elementary streams and a plurality of audio elementary streams, and a time stamp;
demultiplexing each of the plurality of video elementary streams and the plurality of audio elementary streams by demultiplexing the portions of the video elementary streams and the audio elementary streams;
maintaining a clock reference;
queuing each of the plurality of audio elementary streams in a plurality of audio FIFOs corresponding to the plurality of audio elementary streams, wherein each of the plurality of audio FIFOs comprise a front end, and wherein the front end of each of the plurality of audio FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference;
queuing each of the plurality of video elementary streams in a plurality of video FIFOs corresponding to the plurality of video elementary streams, wherein each of the plurality of video FIFOs comprise a front end, and wherein the front end of each of the plurality of video FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference.
13 . The method of claim 12 , further comprising:
decoding selected ones of the plurality of audio elementary streams by decoding portions at the front end of audio FIFOs corresponding to the selected ones of the plurality of audio elementary streams and a newly selected one of the plurality of audio elementary streams by switching from decoding portions at the front end of an audio FIFO corresponding to one of the selected ones of the plurality of audio elementary streams to decoding portions at the front end of a FIFO corresponding to the newly selected one of the plurality of audio elementary streams.
14 . The method of claim 13 , further comprising:
decoding selected ones of the plurality of video elementary streams by decoding portions at the front end of video FIFOs corresponding to the selected ones of the plurality of video elementary streams, while decoding the selected ones of the audio elementary streams and the newly selected audio elementary stream.
15 . The method of claim 14 , wherein decoding selected ones of the plurality of video elementary streams further comprises decompressing the selected ones of the plurality of video elementary streams.
16 . The method of claim 14 , wherein decoding selected ones of the plurality of audio elementary streams further comprises decompressing the selected ones of the plurality of audio elementary streams.
17 . An integrated circuit for decoding data, said integrated circuit comprising:
a program processor for receiving a program stream, said program stream comprising a plurality of packs, each of the packs comprising a portion of one of a plurality video elementary streams and a plurality of audio elementary streams, an identifier identifying the one of the plurality video elementary streams and a plurality of audio elementary streams, and a time stamp, wherein said program processor demultiplexes each of the plurality of video elementary streams and the plurality of audio elementary streams by demultiplexing the portions of the video elementary streams and the audio elementary streams;
a system clock for maintaining a clock reference;
a plurality of audio FIFOs corresponding to the plurality of audio elementary streams for queuing each of the plurality of audio elementary streams, wherein each of the plurality of audio FIFOs comprise a front end, and wherein the front end of each of the plurality of audio FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference; and
a plurality of video FIFOs corresponding to the plurality of video elementary streams for queuing each of the plurality of video elementary streams, wherein each of the plurality of video FIFOs comprise a front end, and wherein the front end of each of the plurality of video FIFOs stores the portion of the corresponding FIFO that comprises a time stamp that is proximate to the clock reference.
18 . The integrated circuit of claim 17 , further comprising:
at least one audio decoder for decoding selected ones of the plurality of audio elementary streams by decoding portions at the front end of audio FIFOs corresponding to the selected ones of the plurality of elementary streams and a newly selected one of the plurality of audio elementary streams by switching from decoding portions at the front end of an audio FIFO corresponding to one of the selected ones of the plurality of audio elementary streams to decoding portions at the front end of an audio FIFO corresponding to the newly selected one of the plurality of audio elementary streams.
19 . The integrated circuit of claim 18 , wherein the at least one video decoder further comprises:
an extractor for receiving the selected ones of the video elementary stream; and
a video decompression engine for decompressing selected ones of the video elementary streams.
20 . The integrated circuit of claim 17 , further comprising:
at least one video decoder for decoding selected ones of the plurality of video elementary streams by decoding portions at the front end of video FIFOs corresponding to the selected ones of the plurality of video elementary streams and a newly selected one of the plurality of video elementary streams by switching from decoding portions at the front end of an video FIFO corresponding to one of the selected ones of the plurality of video elementary streams to decoding portions at the front end of an video FIFO corresponding to the newly selected one of the plurality of video elementary streams.
21 . The integrated circuit of claim 20 , wherein the at least one video decoder further comprises:
an extractor for receiving the selected ones of the video elementary stream; and
a video decompression engine for decompressing selected ones of the elementary streams.