Graphics processing apparatus

1. A graphics processing apparatus comprising:

a main processing unit, which generates at least one rendering command based on an application program;

a main memory, which holds geometry data, texture data, and a graphics command buffer retaining a rendering command sequence of at least one rendering command generated by the main processing unit, the geometry data, the texture data, and the graphics command buffer being memory-mapped to an I/O address space; and

a graphics processing unit, which reads the rendering command sequence retained in the graphics command buffer in the main memory, wherein the memory is outside the graphics processing unit, and executes a rendering process,

wherein the main processing unit comprises:

a main processor, which executes a common process; and

a sub processor, which executes an arithmetic operation relating to graphics and which generates and initializes the graphics command buffer,

wherein graphics processing tasks in the main processing unit are solely performed by the sub processor,

wherein management and reading and writing to and from the graphics command buffer is exclusively controlled by the sub processor, which further exclusively generates the rendering command based on the application program, stores in the graphics command buffer the rendering command that has been generated, generates geometry data and texture data necessary for executing the rendering command that has been generated, and stores the geometry data and the texture data in a respective memory-mapped section of the main memory on behalf of the main processing unit, and

wherein the sub processor communicates information on the rendering command generated with the graphics processing unit and synchronizes updates with the graphics processing unit by reading from or writing to a register of the graphics processing unit.

2. The graphics processing apparatus according to claim 1 , wherein reading from and writing to the graphics command buffer is assisted by a read pointer and a write pointer, respectively, the read pointer pointing to a position in the graphics command buffer from which the rendering command is read by the graphics processing unit next time, the write pointer pointing to a position in the graphics command buffer at which the sub processor completed writing the rendering command last time.

3. The graphics processing apparatus according to claim 1 , wherein the sub processor controls synchronization with the graphics processing unit without intervention by the main processor.

4. The graphics processing apparatus according to claim 1 , wherein the graphics processing unit controls synchronization with the sub processor by interrupting the sub processor, without intervention by the main processor.

5. The graphics processing apparatus according to claim 1 , wherein the sub processor and the graphics processing unit control synchronization with each other by reading or writing data retained in the main memory outside the graphics command buffer, without intervention of the main processor.

6. A graphics processing apparatus comprising:

a main processing unit, which generates at least one rendering command based on an application program;

a main memory, which holds geometry data, texture data, and a plurality of graphics command buffers retaining a rendering command sequence of at least one rendering command generated by the main processing unit, the geometry data, the texture data, and the plurality of graphics command buffers being memory-mapped to an I/O address space; and

a graphics processing unit, which reads the rendering command sequence retained in the plurality of graphics command buffers in the main memory, wherein the main memory is outside the graphics processing unit, and executes a rendering process,

wherein the main processing unit comprises:

a main processor, which executes a common process; and

a plurality of sub processors, which operate independently of each other, wherein each of the plurality of sub processors generates and initializes a respective graphics command buffer,

wherein graphics processing tasks in the main processing unit are solely performed by the plurality of sub processors,

wherein management and reading and writing to and from a respective graphics command buffer among the plurality of graphics command buffers is exclusively controlled by a respective sub processor among the plurality of sub processors, independently of each of the other sub processors, the respective sub processor further exclusively generating the rendering command sequence independently, retaining the generated rendering command sequence in the respective graphics command buffer, and generating jump instructions to link the individual respective graphics command buffers, a jump instruction having a jump destination address set to a head address of the rendering command sequence corresponding to another graphics command buffer on behalf of the main processing unit.

7. The graphics processing apparatus according to claim 6 , wherein the sub processor, which generates the rendering command sequence also generates data necessary for the execution of the rendering command that has been generated and retains the data in the main memory outside the graphics command buffer.

8. The graphics processing apparatus according to claim 6 , wherein another sub processor which is different from one sub processor generating the rendering command sequence generates data necessary for the execution of the rendering command that has been generated, and retains the data in the main memory outside the graphics command buffer.