Control circuit of DC-DC converter
View Patent ↗A control circuit of a DC-DC converter is provided. A mode selection section selects an Active Clamp Forward (ACF) or a Logic Link Control (LLC) mode. A soft start section generates a soft start signal in the ACF and LLC modes. A PWM comparison section compares a current detection signal with a feedback signal, a feedback reference signal and the soft start signal in the ACF mode, and generates a PWM signal based on a comparison result. A selection section selects the PWM signal of the PWM comparison section in the ACF mode. A clock generation section generates a clock signal having a fixed frequency in the ACF mode, and generates a clock signal having a frequency based on an operating current and the soft start signal in the LLC mode. A latch section maintains the PWM signal in response to the clock signal in the ACF mode and maintains the clock signal in the LLC mode.
1. A control circuit of a direct current-direct current converter, comprising:
a mode selection section for selecting an active clamp forward operating mode or a logic link control operating mode;
a soft start section for generating a soft start signal in the active clamp forward operating mode and the logic link control operating mode;
a pulse width modulation comparison section for comparing a current detection signal from a slope compensation section with a feedback signal, a feedback reference signal and the soft start signal when the active clamp forward operating mode is selected, and generating a pulse width modulation signal based on a comparison result;
a selection section for selecting the pulse width modulation signal of the pulse width modulation comparison section when the active clamp forward operating mode is selected;
a clock generation section for generating a clock signal having a preset fixed frequency when the active clamp forward operating mode is selected, and generating a clock signal having a frequency based on an operating current and the soft start signal when the logical link control operating mode is selected; and
a latch section for maintaining the pulse width modulation signal through the selection section in response to the clock signal of the clock generation section when the active clamp forward operating mode is selected, and maintaining the clock signal of the clock generation section when the logical link control operating mode is selected.
2. The control circuit of the direct current-direct current converter of claim 1 , further comprising the slope compensation section for compensating a slope of the current detection signal when the active clamp forward operating mode is selected.
3. The control circuit of the direct current-direct current converter of claim 1 , further comprising an output driver for generating first and second output signals having a dead time by inverting an output signal of the latch section.
4. The control circuit of the direct current-direct current converter of claim 2 , wherein the soft start section includes:
a soft start circuit for generating the soft start signal in the active clamp forward and in logical link control operating modes; and
a voltage-to-current converter, operable upon selection of the logical link control operating mode, for converting the soft start signal of a voltage form into a current form.
5. The control circuit of the direct current-direct current converter of claim 4 , wherein the pulse width modulation comparison section includes:
a plurality of inversion input terminals for respectively receiving the feedback signal, the feedback reference signal and the soft start signal when the active clamp forward operating mode is selected;
a non-inversion input terminal for receiving the current detection signal from the slope compensation section; and
an output terminal for outputting a comparison value by comparing the current detection signal with a smallest value of the feedback signal, the feedback reference signal and the soft start signal.
6. The control circuit of the direct current-direct current converter of claim 4 , wherein the pulse width modulation comparison section includes:
a comparator for comparing the current detection signal from the slope compensation section with a smallest value of the feedback signal, the feedback reference signal and the soft start signal, outputting a high level when the current detection signal is more than the smallest value, and outputting a low level when the current detection signal is not more than the smallest value.
7. The control circuit of the direct current-direct current converter of claim 4 , wherein the clock generation section includes:
a frequency controller for controlling the generation of the clock signal having the preset fixed frequency when the active clamp forward operating mode is selected, and controlling the generation of the clock signal having the frequency based on the operating current and the soft start signal when the logical link control operating mode is selected; and
a current-controlled oscillator for generating the clock signal under control of the frequency controller.
8. The control circuit of the direct current-direct current converter of claim 6 , wherein, when the logical link control operating mode is selected, the frequency controller controls generation of a clock signal having a frequency to be gradually lowered by the operating current if the soft start signal is less than a reference level and controls generation of a clock signal having a preset operating frequency if the soft start signal is more than the reference level.
9. The control circuit of the direct current-direct current converter of claim 1 , wherein the latch section includes:
a reset/set latch for maintaining the pulse width modulation signal through the selection section in response to the clock signal of the clock generation section when the active clamp forward operating mode is selected and maintaining the clock signal of the clock generation section when the logical link control operating mode is selected; and
a logic element for performing a logical AND operation on an output signal of the reset/set latch and the clock signal of the clock generation section.
10. The control circuit of the direct current-direct current converter of claim 3 , wherein the output driver includes:
an output circuit for outputting a signal of the latch section; and
a dead time controller for outputting the first and second output signals having the dead time by inverting the signal from the output circuit.