Thin film transistor array panel and method for manufacturing the same
View Patent ↗A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.
1. A thin film transistor array panel comprising:
a gate electrode including a metal that can be combined with silicon to form silicide;
a semiconductor formed under or over the gate electrode;
a gate insulation layer formed between the gate electrode and the semiconductor;
a source electrode and a drain electrode that contact the semiconductor; and
a pixel electrode connected to the drain electrode,
wherein the gate insulation layer includes a first silicon nitride layer and a second silicon nitride layer interposed between the first silicon nitride layer and the semiconductor, and
wherein a [N—H]/[Si—H] binding number ratio of the first silicon nitride layer is greater than that of the second silicon nitride layer.
2. The thin film transistor array panel of claim 1 , wherein the gate line comprises copper.
3. The thin film transistor array panel of claim 2 , wherein the first silicon nitride layer has a thickness of about 50 to about 600 angstroms (Å).
4. The thin film transistor array panel of claim 2 , wherein the [N—H]/[Si—H] binding number ratio of the first silicon nitride layer is about 20 to about 40, and the [N—H]/[Si—H] binding number ratio of the second silicon nitride layer is about 1.5 to about 2.5.
5. The thin film transistor array panel of claim 1 , further comprising a passivation layer formed on the source electrode and the drain electrode,
wherein the passivation layer includes a third silicon nitride layer and a fourth silicon nitride layer interposed between the third silicon nitride layer and the pixel electrode, and a [N—H]/[Si—H] binding number ratio of the third silicon nitride is greater than that of the fourth silicon nitride.
6. A thin film transistor array panel comprising:
a gate electrode including a metal that can be combined with silicon to form silicide;
a semiconductor formed under or over the gate electrode;
a gate insulation layer interposed between the gate electrode and the semiconductor, wherein the gate insulation layer comprises silicon nitride;
a source electrode and a drain electrode that contact the semiconductor; and
a pixel electrode connected to the drain electrode,
wherein the gate insulation layer comprises a contact unit that contacts the gate electrode, a channel unit that contacts the semiconductor, and a middle unit interposed between the contact unit and the channel unit, and
wherein the contact unit and the middle unit have different [N—H]/[Si—H] binding number ratios.
7. The thin film transistor array panel of claim 6 , wherein the gate electrode comprises copper.
8. The thin film transistor array panel of claim 7 , wherein the [N—H]/[Si—H] binding number ratio of the contact unit of the gate insulation layer is greater than that of the middle unit.
9. The thin film transistor array panel of claim 8 , wherein the [N—H]/[Si—H] binding number ratio of the contact unit is about 20 to about 40, and the [N—H]/[Si—H] binding number ratio of the middle unit is about 1.5 to about 2.5.
10. The thin film transistor array panel of claim 6 , wherein the [N—H]/[Si—H] binding number ratios of the contact unit and the channel unit are greater than that of the middle unit.
11. The thin film transistor array panel of claim 10 , wherein the [N—H]/[Si—H] binding number ratios of the contact unit and the channel unit are about 20 to about 40, and the [N—H]/[Si—H] binding number ratio of the middle unit is about 1.5 to about 2.5.