BJT and method for fabricating the same
View Patent ↗According to one embodiment, a collector electrode including metal is used for a sink region for connecting an n+ type buried layer, so that the sink region can be narrowly formed. Further, an interval between a base region and the collector electrode can be reduced, thereby considerably decreasing the size of the transistor. Furthermore, collector resistance is reduced, so that the performance of the transistor can be improved.
1. A bipolar transistor comprising:
a first conductive buried layer in a surface of a silicon substrate;
an epitaxial layer on the silicon substrate including the first conductive buried layer;
base and emitter regions in a surface of the epitaxial layer, in which the base and emitter regions are spaced apart from each other by a predetermined interval;
an opening formed by selectively removing the epitaxial layer such that a surface of the first conductive buried layer is partially exposed;
a first conductive diffusion region in a surface of the first conductive buried layer corresponding to the opening;
an interlayer dielectric layer formed on an entire surface of the silicon substrate;
contact holes formed simultaneously by selectively removing the interlayer dielectric layer such that the surfaces of the base region, the emitter region, and the first conductive diffusion region are exposed; and
base, emitter, and collector electrodes electrically connected to the base region, the emitter region, and the first conductive diffusion region through the contact holes, respectively;
wherein:
the contact hole for the collector electrode has a width wider than a width of the opening and the remaining contact hole, and forms a step structure.
2. The bipolar transistor as claimed in claim 1 , wherein a width of the collector electrode in the contact hole is wider than a width of the collector electrode in the opening.
3. A method of fabricating a bipolar transistor, the method comprising the steps of:
forming a first conductive buried layer in a surface of a silicon substrate;
forming an epitaxial layer on the silicon substrate including the first conductive buried layer;
forming base and emitter regions in a surface of the epitaxial layer, in which the base and emitter regions are spaced apart from each other by a predetermined interval;
forming an opening by selectively removing the epitaxial layer such that a surface of the first conductive buried layer is partially exposed;
forming a first conductive diffusion region in a surface of the first conductive buried layer corresponding to the opening;
forming an interlayer dielectric layer on an entire surface of the silicon substrate; and
forming contact holes simultaneously by selectively removing the interlayer dielectric layer such that the surfaces of the base region, the emitter region and the first conductive diffusion region are exposed;
wherein:
the contact hole for the first conductive diffusion region has a width wider than a width of the opening and the remaining contact hole;
and forms a step structure.
4. The method as claimed in claim 3 , further comprising a step of forming base, emitter and collector electrodes electrically connected to the base region, the emitter region, and the first conductive diffusion region through the contact holes, respectively.
5. The method as claimed in claim 4 , wherein a width of the collector electrode in the opening is narrower than a width of the collector electrode in the contact hole.