IP Library Granted Patent US 9,207,997
Granted Patent B2
US 9,207,997 · App. 11/930,603 · Granted Dec 8, 2015

Multithreaded lock management

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Quick Facts
Patent No.
US 9,207,997
App. No.
11/930,603
Granted
Dec 8, 2015
Kind
B2
Abstract

Apparatus, systems, and methods may operate to construct a memory barrier to protect a thread-specific use counter by serializing parallel instruction execution. If a reader thread is new and a writer thread is not waiting to access data to be read by the reader thread, the thread-specific use counter is created and associated with a read data structure and a write data structure. The thread-specific use counter may be incremented if a writer thread is not waiting. If the writer thread is waiting to access the data after the thread-specific use counter is created, then the thread-specific use counter is decremented without accessing the data by the reader thread. Otherwise, the data is accessed by the reader thread and then the thread-specific use counter is decremented. Additional apparatus, systems, and methods are disclosed.

Claims (51)

1. An apparatus, comprising:

a memory to store a thread-specific use counter associated with an active reader thread; and

a processor to modify the thread-specific use counter solely via the active reader thread or a thread destruction recovery process, wherein the thread-specific use counter forms a portion of a thread-specific data structure protected by a serializing instruction execution memory barrier, and wherein the thread-specific data structure is linked to a write data structure and a read data structure associated with a writer thread and the active reader thread, respectively, and wherein the active reader thread is configured to release a read mode read-write lock associated with data being accessed after decrementing the thread-specific use counter.

2. The apparatus of claim 1 , wherein the processor is to have read access to the thread-specific use counter via a plurality of reader threads, including the active reader thread.

3. The apparatus of claim 1 , wherein the processor is to have read access to the thread-specific use counter via the writer thread.

4. The apparatus of claim 1 , further comprising:

a memory to store data to be accessed by a plurality of reader threads, including the active reader thread, as long as the thread-specific use counter indicates the active reader thread is still active.

5. The apparatus of claim 1 , wherein the thread-specific use counter associated with the active reader thread is greater than zero.

6. A system, comprising:

a memory to store a thread-specific use counter associated with an active reader thread; and

a plurality of processors to implement a cache coherence protocol, including at least one processor to modify the thread-specific use counter solely via the active reader thread or a thread destruction recovery process, wherein the thread-specific use counter forms a portion of a thread-specific data structure protected by a serializing instruction execution memory barrier, and wherein the thread-specific data structure is linked to a write data structure and a read data structure associated with a writer thread and the active reader thread, respectively, and wherein the active reader thread is configured to release a read mode read-write lock associated with data being accessed after decrementing the thread-specific use counter.

7. The system of claim 6 , wherein each one of the plurality of processors has read access to the write data structure and the read data structure.

8. A method, comprising:

constructing a serializing instruction execution memory barrier to protect a thread-specific use counter by serializing parallel instruction execution by at least one processor;

if a reader thread is new and a writer thread is not waiting to access data to be read by the reader thread, creating the thread-specific use counter associated with a read data structure and a write data structure, and incrementing the thread-specific use counter;

if the writer thread is waiting to access the data after the thread-specific use counter is created, then decrementing the thread-specific use counter without accessing the data by the reader thread; and

otherwise, accessing the data by the reader thread and then releasing, by the reader thread, a read mode read-write lock associated with the data after decrementing the thread-specific use counter.

9. The method of claim 8 , wherein at least one of the read data structure and the write data structure form a portion of a table.

10. The method of claim 8 , wherein the thread-specific use counter forms a portion of a thread-specific data structure including a list linked to a writer hash table based on a thread identifier.

11. The method of claim 8 , comprising:

yielding access to the data, by the reader thread, to the writer thread that is waiting, prior to creation of the thread-specific use counter.

12. The method of claim 11 , comprising:

repeating the yielding until the writer thread has unlocked access to the data and is no longer waiting.

13. The method of claim 8 , comprising:

using a cache coherent protocol to notify processors other than the at least one processor as to the status of the thread-specific use counter.

14. The method of claim 8 , wherein the at least one processor is a member of a group of processors, and wherein the memory barrier is applied across the group of processors.

15. The method of claim 8 , comprising:

after incrementing the thread-specific use counter, setting a read mode read-write lock associated with the data.

16. The method of claim 8 , comprising:

accessing the thread-specific use counter via the read data structure using a plurality of active reader threads associated with individual thread-specific data structures linked to the read data structure.

17. The method of claim 8 , comprising:

accessing the read data structure by the writer thread to determine whether any active threads exist.

18. The method of claim 8 , comprising:

linking the thread-specific data structure to the read data structure and the write data structure using a hash mechanism.

19. The method of claim 8 , comprising:

accessing the read data structure by a call-back function after a specified time or upon destruction of the reader thread to remove a link to the thread-specific data structure.

20. A method, comprising:

indicating a writer thread is waiting to access data;

determining a number of active reader threads by accessing thread-specific data forming a portion of a thread-specific data structure protected by a serializing instruction execution memory barrier, wherein the thread-specific data structure is linked to a write data structure and a read data structure; and

if the number of active reader threads is not greater than zero, indicating that the writer thread is no longer waiting to access the data and acquiring a writer mutex to manage serial access to the write data structure,

wherein at least one of the number of active reader threads is configured to release a read mode read-write lock associated with the data after decrementing the thread-specific data.

21. The method of claim 20 , comprising:

if the number of active threads is greater than zero, yielding access to the data to the active reader threads until the number of active threads release their read mode read-write locks associated with the data.

22. The method of claim 20 , wherein acquiring the writer mutex includes setting a write mode read-write lock associated with the data.

23. The method of claim 20 , comprising:

accessing the write data structure after creating the thread-specific data structure, by the writer thread, by new reader threads, and by a call-back function upon destruction of one of the active reader threads.

24. The method of claim 20 , comprising:

accessing the write data structure via a write mode using a writer mutex.

25. The method of claim 20 , comprising:

releasing a read-write lock by one of the active reader threads or the writer thread; and

checking status of a writer-running variable to determine whether the one of the active reader threads or the writer thread has released the read-write lock.

Assignments (16)
RELEASE OF SECURITY INTEREST REEL/FRAME 035656/0251 Recorded Feb 2, 2023
From: JPMORGAN CHASE BANK, N.A.
To: BORLAND SOFTWARE CORPORATION; ATTACHMATE CORPORATION; NETIQ CORPORATION; MICRO FOCUS (US), INC.; MICRO FOCUS SOFTWARE INC. (F/K/A NOVELL, INC.)
Reel/Frame 062623/0009 →
RELEASE OF SECURITY INTEREST REEL/FRAME 044183/0718 Recorded Feb 2, 2023
From: JPMORGAN CHASE BANK, N.A.
To: MICRO FOCUS LLC (F/K/A ENTIT SOFTWARE LLC); BORLAND SOFTWARE CORPORATION; MICRO FOCUS (US), INC.; SERENA SOFTWARE, INC; ATTACHMATE CORPORATION; MICRO FOCUS SOFTWARE INC. (F/K/A NOVELL, INC.); NETIQ CORPORATION
Reel/Frame 062746/0399 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT TYPO IN APPLICATION NUMBER 10708121 WHICH SHOULD BE 10708021 PREVIOUSLY RECORDED ON REEL 042388 FRAME 0386. ASSIGNOR(S) HEREBY CONFIRMS THE NOTICE OF SUCCESSION OF AGENCY. Recorded Jul 26, 2018
From: BANK OF AMERICA, N.A., AS PRIOR AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 048793/0832 →
SECURITY INTEREST Recorded Oct 11, 2017
From: ATTACHMATE CORPORATION; BORLAND SOFTWARE CORPORATION; NETIQ CORPORATION; MICRO FOCUS (US), INC.; MICRO FOCUS SOFTWARE, INC.; ENTIT SOFTWARE LLC; ARCSIGHT, LLC; SERENA SOFTWARE, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 044183/0718 →
NOTICE OF SUCCESSION OF AGENCY Recorded May 2, 2017
From: BANK OF AMERICA, N.A., AS PRIOR AGENT
To: JPMORGAN CHASE BANK, N.A., AS SUCCESSOR AGENT
Reel/Frame 042388/0386 →
CHANGE OF NAME Recorded Sep 13, 2016
From: NOVELL, INC.
To: MICRO FOCUS SOFTWARE INC.
Reel/Frame 040020/0703 →
SECURITY INTEREST Recorded May 13, 2015
From: MICRO FOCUS (US), INC.; BORLAND SOFTWARE CORPORATION; ATTACHMATE CORPORATION; NETIQ CORPORATION; NOVELL, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 035656/0251 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 028252/0316 Recorded Nov 24, 2014
From: CREDIT SUISSE AG
To: NOVELL, INC.
Reel/Frame 034469/0057 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 028252/0216 Recorded Nov 24, 2014
From: CREDIT SUISSE AG
To: NOVELL, INC.
Reel/Frame 034470/0680 →
GRANT OF PATENT SECURITY INTEREST FIRST LIEN Recorded May 23, 2012
From: NOVELL, INC.
To: CREDIT SUISSE AG, AS COLLATERAL AGENT
Reel/Frame 028252/0216 →
GRANT OF PATENT SECURITY INTEREST SECOND LIEN Recorded May 23, 2012
From: NOVELL, INC.
To: CREDIT SUISSE AG, AS COLLATERAL AGENT
Reel/Frame 028252/0316 →
RELEASE OF SECURITY IN PATENTS SECOND LIEN (RELEASES RF 026275/0018 AND 027290/0983) Recorded May 22, 2012
From: CREDIT SUISSE AG, AS COLLATERAL AGENT
To: NOVELL, INC.
Reel/Frame 028252/0154 →
RELEASE OF SECURITY INTEREST IN PATENTS FIRST LIEN (RELEASES RF 026270/0001 AND 027289/0727) Recorded May 22, 2012
From: CREDIT SUISSE AG, AS COLLATERAL AGENT
To: NOVELL, INC.
Reel/Frame 028252/0077 →
GRANT OF PATENT SECURITY INTEREST (SECOND LIEN) Recorded May 13, 2011
From: NOVELL, INC.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 026275/0018 →
GRANT OF PATENT SECURITY INTEREST Recorded May 12, 2011
From: NOVELL, INC.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 026270/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2008
From: RATHI, PRADEEP KUMAR
To: NOVELL, INC.
Reel/Frame 020441/0607 →