Method for manufacturing a signal line, thin film transistor panel, and method for manufacturing the thin film transistor panel

1. A method for manufacturing a signal line, comprising:

forming a lower layer including at least one metal layer;

depositing an upper layer including at least Cu metal on the lower layer;

forming a photoresist film on the upper layer;

selectively wet-etching the upper layer by using the photoresist film as an etch mask; and

dry-etching the lower layer by using the photoresist film as an etch mask,

wherein an etchant for the wet-etching includes ethylene glycol, sulfuric acid (H2SO4), nitric acid, and deionized water.

2. The method of claim 1 , wherein the etchant for the wet-etching includes ethylene glycol at about 0.1 wt %-about 30 wt %, sulfuric acid (H2SO4) at about 0.1 wt %-about 30 wt %, nitric acid at about 1.0 wt %-about 70 wt %, and deionized water.

3. The method of claim 1 , wherein the lower layer includes a conductive layer including at least one of Cr, Al, and Mo.

4. A method for forming a thin film transistor array panel, comprising;

forming a gate line on a substrate;

sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line;

forming a photoresist film on the conductor layer;

patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a thinner thickness than the first portion;

etching the upper layer and the lower layer by using the photoresist pattern as an etch mask;

etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor;

removing the second portion of the photoresist pattern by using an etch back process;

selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask;

dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers; and

forming a pixel electrode connected to the drain electrode,

wherein an etchant for selectively wet-etching the upper layer includes ethylene glycol, sulfuric acid (H2SO4), nitric acid, and deionized water.

5. The method of claim 4 , wherein the first portion of the photoresist pattern is aligned with a region corresponding to the data line and the drain electrode.

6. The method of claim 4 , wherein the second portion of the photoresist pattern is aligned with a channel region between a source electrode of the data line and the drain electrode.

7. The method of claim 4 , wherein the upper layer includes Cu and the lower layer includes one of Mo, Cr, and Al.

8. The method of claim 4 , wherein the upper layer and the lower layer are etched under different etching conditions.

9. The method of claim 4 , wherein the upper layer and the lower layer are etched under the same etching conditions.

10. The method of claim 9 , wherein an etchant for etching the upper layer and the lower layer together includes hydrogen peroxide.

11. The method of claim 4 , wherein the etch back process is executed before the completion of the semiconductor.

12. The method of claim 11 , wherein the upper layer and the lower layer are etched under different etching conditions.

13. The method of claim 12 , wherein the etch back process is executed before dry-etching of the lower layer.

14. The method of claim 11 , wherein the upper layer and the lower layer are etched under the same etching conditions.

15. The method of claim 14 , wherein an etchant for etching the upper layer and the lower layer together includes hydrogen peroxide.

16. The method of claim 4 , wherein the gate line includes a single layer of a conductive layer made of Cu, or multi-layers including the single layer.