Array substrate, display apparatus having the same
View Patent ↗An array substrate includes a base substrate which includes a display area and a peripheral area adjacent to the display area, a plurality of fan-out lines arranged in the peripheral area to receive a driving signal from an exterior source, at least one fan-out line among the plurality of fan-out lines arranged on a different layer from a layer on which remaining fan-out lines of the plurality of fan-out lines are arranged, a plurality of signal lines arranged in the display area to receive the driving signal from the plurality of fan-out lines and a pixel array arranged in the display area to receive the driving signal from the plurality of signal lines.
1. An array substrate comprising:
a base substrate on which a display area for displaying-to display an image thereon and a peripheral area adjacent to the display area are defined;
a plurality of fan-out lines arranged in the peripheral area to receive a driving signal from an external source, all of the fan-out lines being alternately arranged on two different layers so that two adjacent fan-out lines among the fan-out lines are arranged on different layers;
a plurality of signal lines arranged in the display area to receive the driving signal from the fan-out lines; and
a pixel array arranged in the display area to receive the driving signal from the signal lines.
2. An array substrate comprising:
a base substrate on which a display area to display an image thereon and a peripheral area adjacent to the display area are defined;
a plurality of fan-out lines arranged in the peripheral area to receive a driving signal from an external source, all of the fan-out lines being alternately arrange on two different layers so that odd-numbered fan-out lines among the fan-out lines are arranged on a different layer from a layer on which even-numbered fan-out lines among the fan-out lines are arranged;
a plurality of signal lines arranged in the display area to receive the driving signal from the fan-out lines; and
a pixel array arranged in the display area to receive the driving signal from the signal lines.
3. The array substrate of claim 2 , wherein the odd-numbered fan-out lines appear to make contact with the even-numbered fan-out lines in a plan view.
4. The array substrate of claim 2 , wherein two adjacent fan-out lines arranged on a same layer are spaced apart from each other at a predetermined distance, and each of the odd-numbered fan-out lines is overlapped with an adjacent even-numbered fan-out line among the even-numbered fan-out lines.
5. The array substrate of claim 2 , wherein either the odd-numbered fan-out lines or the even-numbered fan-out lines are arranged on a same layer as a layer on which the signal lines are arranged.
6. The array substrate of claim 5 , wherein the signal lines are arranged in a one-to-one correspondence with the fan-out lines.
7. The array substrate of claim 6 , further comprising at least one insulation layer covering the odd-numbered fan-out lines and the even-numbered fan-out lines, and the at least one insulation layer insulating the odd-numbered fan-out lines from the even-numbered fan-out lines.
8. The array substrate of claim 7 , wherein the pixel array comprises:
a plurality of thin film transistors arranged in the display area in a matrix configuration, the thin film transistors connected to the signal lines to receive the driving signal; and
a plurality of pixel electrodes arranged in the display area in a matrix configuration, the pixel electrodes being arranged on the at least one insulation layer and electrically connected to the thin film transistors.
9. The array substrate of claim 8 , further comprising at least one connection electrode arranged on the insulation layer to electrically connect the fan-out lines, which are arranged on a different layer from the layer on which the signal lines are arranged, with corresponding signal lines among the signal lines.
10. The array substrate of claim 9 , wherein the insulation layer is partially removed to provide a through hole through which the fan-out lines arranged on the different layer from the plurality-of signal lines are exposed, the at least one connection electrode is electrically connected to the fan-out lines arranged on the different layer from the signal lines through the through hole.
11. The array substrate of claim 9 , wherein the at least one connection electrode is arranged on a same layer as a layer on which the pixel electrodes are arranged.
12. The array substrate of claim 8 , wherein the fan-out lines arranged on the different layer from the signal lines are arranged on a same layer as a layer on which the pixel electrodes are arranged.
13. The array substrate of claim 12 , wherein the fan-out lines arranged on the same layer as the layer on which the pixel electrodes are arranged comprise a same material as that of the pixel electrodes.
14. The array substrate of claim 5 , wherein the odd-numbered fan-out line and the even-numbered fan-out line adjacent to the odd-numbered fan-out line appear to make contact with each other in a plan view.
15. The array substrate of claim 5 , wherein two adjacent fan-out lines arranged on a same layer are spaced apart from each other at a predetermined distance, and each of the odd-numbered fan-out lines is overlapped with an adjacent even-numbered fan-out line among the even-numbered fan-out lines.
16. The array substrate of claim 2 , wherein the odd-numbered fan-out lines comprise a different material from that of the even-numbered fan-out lines.
17. The array substrate of claim 2 , wherein each of fan-out line of the fan-out lines is partially bent to include a serpentine portion.
18. The array substrate of claim 17 , wherein the serpentine portion of each of the fan-out lines comprises:
a first serpentine portion extending in a direction along which the fan-out lines are arranged; and
a second serpentine portion extending from the first serpentine portion to a longitudinal direction of the fan-out lines.
19. The array substrate of claim 18 , wherein two adjacent fan-out lines arranged on a same layer are spaced apart from each other at a predetermined distance, and the second serpentine portion of each of the odd-numbered fan-out lines is overlapped with the second serpentine portion of an adjacent even-numbered fan-out line among the even-numbered fan-out lines.
20. The array substrate of claim 19 , wherein the second serpentine portion of two adjacent odd-numbered fan-out lines is overlapped with different second serpentine portions of the even-numbered fan out lines.
21. The array substrate of claim 19 , wherein the first serpentine portion of the odd-numbered fan-out lines and the first serpentine portion of the even-numbered fan-out lines adjacent to the odd-numbered fan-out lines are alternately arranged in a plan view.
22. The array substrate of claim 17 , wherein the serpentine portion of the odd-numbered fan-out lines and the serpentine portion of the even-numbered fan-out lines adjacent to the odd-numbered fan-out lines are alternately positioned along a direction in which the plurality of fan-out lines are arranged, and the serpentine portion of the odd-numbered fan-out lines and the serpentine portion of the even-numbered fan-out lines adjacent to the odd-numbered fan-out lines appear to make contact with each other in a plan view.
23. The array substrate of claim 17 , wherein either the odd-numbered fan-out lines or the even-numbered fan-out lines are arranged on a same layer as a layer on which the signal lines are arranged.