Method and apparatus for segmented sequential storage

1. A method, comprising:

providing a microprocessor, the microprocessor including at least:

two or more execution clusters, at least two of the two or more execution clusters including at least one first level stage, the at least one first level stage including one or more of at least one store buffer, at least one register file, or at least one data cache; and

an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage;

dividing the inter-cluster second level stage into a plurality of segments;

dynamically allocating the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time;

sequentially associating the first and second segments via one or more pointers; and

responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, searching at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments,

wherein the dividing, allocating, associating, and searching are implemented at least partially using at least one of (i) at least some hardware blocks of the provided microprocessor or (ii) at least some microcode of the provided microprocessor.

2. A microprocessor, comprising:

one or more CPU cores including at least:

two or more execution clusters, at least two of the two or more execution clusters including at least one first level stage, the at least one first level stage including one or more of at least one store buffer, at least one register file, or at least one data cache;

an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage; and

circuitry configured to at least:

divide the inter-cluster second level stage into a plurality of segments;

dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time;

sequentially associate the first and second segments via one or more pointers; and

responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, search at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments,

wherein the circuitry is at least partially implemented using at least one of (i) at least some hardware blocks of the microprocessor or (ii) at least some microcode of the microprocessor.

3. A microprocessor, comprising:

at least one store of microcode;

two or more execution clusters, at least two of the two or more execution clusters including at least one first level stage, the at least one first level stage including one or more of at least one store buffer, at least one register file, or at least one data cache;

an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage; and

circuitry configured to execute at least some microcode of the at least one store to at least:

divide the inter-cluster second level stage into a plurality of segments;

dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time;

sequentially associate the first and second segments via one or more pointers; and

responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, search at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments.

4. The microprocessor of claim 3 , further comprising:

the microprocessor capable of executing one or more instructions fetched from outside the microprocessor at least partially using at least some microcode of the provided microprocessor.

5. The microprocessor of claim 3 , wherein the inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage comprises:

an inter-cluster second level stage including at least one non-circular data structure capable of being divided into one or more segments, the one or more segments capable of including at least one or more entries.

6. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least divide the inter-cluster second level stage into a plurality of segments comprises:

circuitry configured to execute at least some microcode of the at least one store to at least divide the inter-cluster second level stage into one or more segments, the one or more segments capable of including at least one or more entries.

7. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least divide the inter-cluster second level stage into a plurality of segments comprises:

circuitry configured to execute at least some microcode of the at least one store to at least divide the inter-cluster second level stage into one or more segments, the one or more segments capable of receiving at least one or more contents.

8. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least divide the inter-cluster second level stage into a plurality of segments comprises:

circuitry configured to execute at least some microcode of the at least one store to at least set at least one of a pre-set or discrete size for one or more of segments or chunks of memory associated with the inter-cluster second level stage to be allocated.

9. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

circuitry configured to execute at least some microcode of the at least one store to at least allocate one or more segments randomly from within a heap.

10. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

circuitry configured to execute at least some microcode of the at least one store to at least allocate one or more segments randomly from within a heap; and

circuitry configured to execute at least some microcode of the at least one store to at least link the one or more segments into a chain associated with a current thread.

11. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate at least one segment; and

circuitry configured to execute at least some microcode of the at least one store to at least sequentially allocate one or more entries associated with the at least one segment.

12. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate at least one segment, wherein the at least one segment is discontiguous in the inter-cluster second level stage.

13. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

circuitry configured to execute at least some microcode of the at least one store to at least dynamically allocate the plurality of segments, including at least allocating at least one of a single wrap bit or multiple wrap bits.

14. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least sequentially associate the first and second segments via one or more pointers comprises:

circuitry configured to execute at least some microcode of the at least one store to at least store at least some sequential allocation information for one or more allocated segments in a data structure that is auxiliary to the inter-cluster second level stage.

15. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least sequentially associate the first and second segments via one or more pointers comprises:

circuitry configured to execute at least some microcode of the at least one store to at least store at least some sequential allocation information for one or more allocated segments in the one or more allocated segments.

16. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store to at least, responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, searching at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments comprises:

circuitry configured to execute at least some microcode of the at least one store to at least, responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, traverse, using the one or more pointers associating the first and second segments, to find a correct address in an enclosing heap.

17. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store further comprises:

circuitry configured to execute at least some microcode of the at least one store to at least dynamically change a size of at least one allocated segment.

18. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store further comprises:

circuitry configured to execute at least some microcode of the at least one store to at least deallocate at least one of the first segment or the second segment responsive to at least one of (i) a request to deallocate or (ii) a kill time associated with the at least one of the first segment or the second segment.

19. The microprocessor of claim 3 , wherein circuitry configured to execute at least some microcode of the at least one store further comprises:

circuitry configured to execute at least some microcode of the at least one store to at least, responsive to a request for at least a portion of the at least one content of the at least one first level stage at the second time, search for the at least one content of the at least one first level stage at the second time at least partially using one or more pointers associated with the plurality of segments.

20. The method of claim 1 , wherein providing a microprocessor, the microprocessor including at least an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage comprises:

providing a microprocessor, the microprocessor including at least an inter-cluster second level stage including at least one non-circular data structure capable of being divided into one or more segments, the one or more segments capable of including at least one or more entries.

21. The method of claim 1 , wherein dividing the inter-cluster second level stage into a plurality of segments comprises:

dividing the inter-cluster second level stage into one or more segments, the one or more segments capable of including at least one or more entries.

22. The method of claim 1 , wherein dividing the inter-cluster second level stage into a plurality of segments comprises:

dividing the inter-cluster second level stage into one or more segments, the one or more segments capable of receiving at least one or more contents.

23. The method of claim 1 , wherein dynamically allocating the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

allocating one or more segments randomly from within a heap.

24. The method of claim 1 , wherein dynamically allocating the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

dynamically allocating at least one segment; and

sequentially allocating one or more entries associated with the at least one segment.

25. The method of claim 1 , wherein dynamically allocating the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time comprises:

dynamically allocating at least one segment, wherein the at least one segment is discontiguous in the inter-cluster second level stage.

26. The method of claim 1 , wherein sequentially associating the first and second segments via one or more pointers comprises:

storing at least some sequential allocation information for one or more allocated segments in a data structure that is auxiliary to the inter-cluster second level stage.

27. The method of claim 1 , wherein sequentially associating the first and second segments via one or more pointers comprises:

storing at least some sequential allocation information for one or more allocated segments in the one or more allocated segments.

28. The method of claim 1 , wherein responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, searching at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments comprises:

responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, traversing, using the one or more pointers associating the first and second segments, to find a correct address in an enclosing heap.

29. The method of claim 1 , further comprising:

dynamically changing a size of at least one allocated segment.

30. The method of claim 1 , further comprising:

responsive to a request for at least a portion of the at least one content of the at least one first level stage at the second time, searching for the at least one content of the at least one first level stage at the second time at least partially using one or more pointers associated with the plurality of segments.