Method and apparatus for screening bit line of a static random access memory (SRAM) for excessive leakage current
View Patent ↗Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method including: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage.
1. A method of testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method comprising:
preventing a write driver circuit from significantly pulling the BLT towards a supply voltage;
preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage;
preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and
comparing the voltage of the BLT under the foregoing conditions to a threshold voltage.
2. The method of claim 1 , further comprising: determining that the SRAM cell includes significant leakage current when the voltage of the BLT is below the threshold voltage.
3. The method of claim 1 , further comprising: determining that the SRAM cell includes significant leakage current when the voltage of the BLT drops linearly below the threshold voltage.
4. A method of testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method comprising:
preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and
comparing the voltage of the BLT under at least the foregoing condition to a threshold voltage.
5. The method of claim 4 , further comprising: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage prior to the comparing step.
6. The method of claim 4 , further comprising: preventing a pre-charge circuit from significantly pulling the BLT towards a supply voltage prior to the comparing step.
7. The method of claim 4 , further comprising: determining that the SRAM cell includes significant leakage current when the voltage of the BLT is below the threshold voltage.
8. The method of claim 4 , further comprising: determining that the SRAM cell includes significant leakage current when the voltage of the BLT drops linearly below the threshold voltage.