Thin film transistor, manufacturing method thereof, and TFT LCD using the same
View Patent ↗A thin film transistor (TFT) that comprises a gate electrode on a substrate, a gate insulation layer on the gate electrode, an active layer having a source region, a drain region, and a channel region on the gate insulation layer, and a source electrode and a drain electrode formed over the source region and drain region of the active layer respectively and facing each other with respect to the channel region. The profile of channel region between the source electrode and drain electrode is changed in a bend line. A method for forming the TFT is also provided.
1. A thin film transistor (TFT), comprising:
a gate electrode formed over a substrate;
a gate insulation layer formed over the gate electrode;
an active layer having a source region, a drain region, and a channel region and formed on the gate insulation layer; and
a source electrode and a drain electrode formed over the source region and drain region of the active layer respectively and opposing each other with respect to the channel region,
wherein the profile of the channel region between the source electrode and the drain electrode is changed in a bend line having a plurality of undulation, each undulation of the bend line having at least one of an ascending edge and a descending edge, and each undulation of the bend line further comprises a plurality of steps in the ascending edge and a plurality of steps in the descending edge.
2. The TFT of claim 1 , wherein the number of undulation in the bend line is N, where N≧1.
3. The TFT of claim 1 , wherein the gate electrode and the data line are formed of a material selected from the group consisting of Mo, Al, AlNi alloy, MoW alloy, Cr, Cu, and any combination thereof in a structure selected from the group consisting of a single layer structure and a multiple layer structure.
4. The TFT of claim 1 , wherein the gate insulation layer is formed of a material selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.
5. The TFT of claim 1 , wherein the active layer is amorphous silicon (a-Si).
6. A method for forming a thin film transistor (TFT), comprising:
forming a gale electrode over a substrate;
forming a gate insulation layer over the gate electrode;
forming an active layer having a source region, a drain region and a channel region on the gate insulation layer; and
forming a source electrode and a drain electrode over the source region and drain region of the active layer, respectively, the source electrode and the drain electrode opposing with respect to the channel region;
wherein the profile of the channel region between the source electrode and drain electrodes is changed in a bend line having a plurality of undulation, each undulation of the bend line having at least one of an ascending edge and a descending edge, and each undulation of the bend line further comprises a plurality of steps in the ascending edge and a plurality of steps in the descending edge.
7. The method of claim 6 , wherein the source electrode and the drain electrode are patterned by an exposure and etching process with a mask, and the profile of the mask corresponding to the channel region is changed in the bend line.
8. The method of claim 6 , wherein the number of undulations in the bend line is N, where N≧1.
9. The method of claim 6 , wherein the gate electrode and the data line are formed of a material selected from the group consisting of Mo, Al, AlNi alloy, MoW alloy, Cr, Cu, and any combination thereof in a structure selected from the group consisting of a single layer structure and a multiple layer structure.
10. The method of claim 6 , wherein the gate insulation layer is formed of a material selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.
11. The method of claim 6 , wherein the active layer is amorphous silicon (a-Si).
12. The method of claim 6 , further comprising after forming the source and drain electrode, forming a passivation layer on the substrate and patterning the passivation layer to form a via hole over one of the source and drain electrodes.
13. A TFT LCD, comprising:
a substrate;
a gate line and a data line formed on the substrate and crossing each other to define a sub-pixel region;
a pixel electrode formed in the sub-pixel region; and
a TFT according to claim 1 , formed at where the gate line and the data line cross,
wherein the gate electrode of the TFT is connected with the gate line, one of the source and drain electrodes is connected with the data line, and the other one of the source and drain electrodes is connected with the pixel electrode.