Controller and driver communication for switching regulators
View Patent ↗Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.
1. A method of communicating mode information for operation of a switching regulator between a pulse width modulation (PWM) controller and at least one output stage driver, said driver coupled to at least one output switch which drives a load, comprising:
receiving a mode indicating signal at said controller, said mode indicating signal operable to indicate intervals of time when said load is a low power mode;
determining when said load is in said low power mode based on said mode indicating signal;
responsive to said determining, said controller generating a PWM mode signal comprising at least three (3) different levels including at least one intermediate level and coupling said PWM mode signal to an input of said driver; and
switching said regulator into at least one low power operational mode based on said PWM mode signal.
2. The method of claim 1 , wherein said low power operational mode comprises at least one of a diode emulation mode, phase dropping mode and a diode braking mode.
3. The method of claim 1 , wherein a transition of said PWM mode signal between a high or low level and said intermediate level is used for triggering said switching.
4. The method of claim 2 , further comprising initiating said diode braking mode when said PWM mode signal transitions from said high level to said intermediate level.
5. The method of claim 1 , wherein said switching comprises identifying when said PWM mode signal remains at said intermediate level for more than a predetermined period of time.
6. The method of claim 1 , wherein said load comprises a microprocessor, said mode indicating signal being provided by said microprocessor.
7. The method of claim 1 , wherein said PWM mode signal comprises a repetitive pattern which begins at a transition from a high level to a low level, reaches said intermediate level after a first time, and transitions from said intermediate level to said high level at a second time, said second time after said first time.