Self-supporting simplex packets
View Patent ↗Existing message fields and/or message parameters are configured to facilitate the packet and message synchronization and decoding tasks that conventionally rely upon a known bit sequence in each packet, thereby eliminating the need for a predefined message preamble in each packet. In example embodiments, the unique identifier of each transmitter is structured to facilitate determination of bit polarity and the start of each packet; packet sequence numbers use an unconventional counting sequence to assure synchronizing bit transitions; and so on. Other techniques, such as the use of run-length limited (RLL) message encoding, or 8b/10b encoding, to assure within-packet bit transitions, are also used to enhance clock synchronization and proper header location determination.
1. A method of decoding a packet that does not include a preamble of known bit values, comprising:
at a device configured to decode the packet: despreading the packet using a spreading code,
identifying a header of the packet that includes a sequence of bit transitions,
identifying a body of the packet that includes information that has been transmitted by a transmitter, wherein identifying the header includes identifying a start of the packet based on the sequence of bit transitions,
determining a first bit transition rate based on transitions in the header,
identifying an end of packet sequence,
determining a second bit transition rate based on transitions in the end of packet sequence, and
estimating a bit transition rate for decoding bits in the body of the packet based on the first and second bit transition rates.
2. The method of claim 1 , wherein the sequence of bit transitions identifies a transmitter of the packet.
3. The method of claim 1 , wherein the end of packet sequence corresponds to an error correction code.
4. The method of claim 1 , including determining a polarity of bits in the packet based on the sequence of bit transitions.
5. The method of claim 1 , including synchronizing a demodulation of the packet based on the sequence of bit transitions.
6. A receiver comprising:
a receive buffer that is configured to receive a composite signal,
a phase detector that is configured to detect a code-phase of a message that does not include a sequence of known bit values,
a demodulator that is configured to:
identify a header of the packet that includes a sequence of bit transitions,
identify a start of the packet based on the sequence of bit transitions,
identify a body of the packet that includes information that has been transmitted
by a transmitter,
determine a first bit transition rate based on the bit transitions in the header,
identify an end of packet sequence,
determine a second bit transition rate based on transitions in the end of packet sequence, and
determine a bit transition rate for decoding bits in the body of the packet based on the first and second bit transition rates.
7. The receiver of claim 6 , wherein
the sequence of bit transitions identifies a transmitter of the packet.
8. The receiver of claim 6 , wherein
the demodulator is configured to determine a polarity of bits in the packet based on the sequence of bit transitions.