Thin film transistor array panel for liquid crystal display and method of manufacturing the same
View Patent ↗A method for manufacturing a thin film transistor array panel is disclosed. A gate wiring pattern is formed on an insulating substrate. A gate insulating layer is formed on the gate wiring pattern. A semiconductor pattern is formed on the gate insulating layer. A transparent conductive layer is formed on the gate insulating layer. The transparent conductive layer is patterned to form a pixel electrode. An opening is formed at a circumference of the pixel electrode. The opening minimizes misalignment during the manufacturing process and prevents shorts between a data line and the pixel electrode.
1. A thin film transistor array panel for a liquid crystal display, comprising:
a insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer covering the gate line;
a data line formed on the gate insulating layer and crossing the gate line to define a pixel;
a passivation layer covering the data line;
a pixel electrode formed on the passivation layer
and electrically connected to the data line;
wherein the gate insulating layer has a first opening, and the passivation layer has a second opening exposing the first opening,
wherein the first opening and second opening are located at an edge region of the pixel.
2. The thin film transistor array panel of claim 1 , wherein the opening is disposed between the pixel electrode and the gate line.
3. The thin film transistor array panel of claim 1 , wherein the opening is disposed between the pixel electrode and the data line.
4. A thin film transistor array panel for a liquid crystal display, comprising:
a insulating substrate;
a gate line formed on the insulating substrate;
a gate insulating layer covering the gate line;
a data line formed on the gate insulating layer and crossing the gate line to define a pixel;
a semiconductor pattern formed on the gate insulating layer;
a source electrode and a drain electrode formed on the semiconductor pattern;
a passivation layer covering the date line, the source electrode and the drain electrode, and having a contact hole exposing the drain electrode; and,
a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole,
wherein the gate insulating layer has a first opening, and the passivation layer has a second opening exposing the first opening,
wherein the first opening and the second opening are located at an edge region of the pixel.
5. The thin film transistor array panel of claim 1 , wherein the first opening and the second opening substantially have the same area.
6. The thin film transistor array panel of claim 4 , wherein the first opening and the second opening substantially have the same area.