IP Library Granted Patent US 8,095,854
Granted Patent B2
US 8,095,854 · App. 11/938,016 · Granted Jan 10, 2012

Method and system for generating low density parity check codes

Assignee: DTVG Licensing, Inc.
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Quick Facts
Patent No.
US 8,095,854
App. No.
11/938,016
Granted
Jan 10, 2012
Kind
B2
Abstract

An approach for generating a structured Low Density Parity Check (LDPC) codes is provided. Structure of the LDPC codes is provided by restricting a certain part of the parity check matrix to be lower triangular, hence enabling a very simple encoding method that does not require the generator matrix of the code. The approach can also exploit the unequal error protecting capability of LDPC codes on transmitted bits to provide extra error protection to more vulnerable bits of high order modulation constellations (such as 8-PSK (Phase Shift Keying)).

Claims (13)

1. A method comprising:

encoding information bits according to a linear block code to generate encoded bits;

transforming the coded bits by mapping bits of a signal constellation having an order of at least four to bit nodes of a parity check matrix corresponding to a linear block code,

wherein bits of the signal constellation that are more vulnerable to channel errors are mapped to bit nodes of the parity check matrix with a number of edges no less than bit nodes mapped to bits of the signal constellation that are less vulnerable to channel errors;

modulating the transformed coded bits according to the signal constellation to generate a modulated signal; and

transmitting the modulated signal.

2. A method according to claim 1 ,

wherein the bits of the signal constellation that are more vulnerable to channel errors are mapped to bit nodes with at least three edges.

3. A method according to claim 2 , wherein the signal constellation comprises at least one of 8-PSK (Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying).

4. A receiver configured to receive a signal representing the linear block code in accordance with claim 2 .

5. A method according to claim 1 , wherein the signal constellation comprises at least one of 8-PSK (Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying).

6. A receiver configured to receive a signal representing the linear block code in accordance with claim 1 .

7. A transmitter configured to implement the method of claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2009
From: HUGHES ELECTRONICS CORPORATION
To: DTVG LICENSING, INC.
Reel/Frame 022668/0373 →
Continuity (7)
Division 10353230 · Jan 28, 2003
Provisional Application 60398760 · Jul 26, 2002
Provisional Application 60403812 · Aug 15, 2002
Provisional Application 60421505 · Oct 25, 2002
Provisional Application 60421999 · Oct 29, 2002
Provisional Application 60423710 · Nov 4, 2002
Related Publication 20080082895A1 · Apr 3, 2008