Method of fabricating semiconductor device
View Patent ↗An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and′ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12 , so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
1. A method of fabricating a semiconductor device, comprising steps of:
(a) forming a gate electrode of an n-channel MISFET over an element isolation region of a first semiconductor region of p-type conductivity formed in a semiconductor body, and a gate electrode of a p-channel MISFET over a main surface of a second semiconductor region of n-type conductivity formed in said semiconductor body,
wherein the element forming region is defined by a shallow groove isolation layer such that the shallow groove isolation layer is formed by a CMP method, and
wherein a gate length of each of said gate electrodes is less than 200 nm;
(b) after said step (a), implanting ions in said first semiconductor region to form a third semiconductor region of n-type conductivity;
(c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
(d) after said step (c), implanting ions in a first region in said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
(e) after said step (c), implanting ions in a second region deeper than said first region in said first semiconductor region to form a fifth semiconductor region of n-type conductivity; and
(f) after said steps (d) and (e), forming a cobalt-silicide layer in said fourth semiconductor region,
wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
wherein said gate electrode of said n-channel MISFET is an N-type gate electrode, and
wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.
2. A method of fabricating a semiconductor device according to claim 1 , wherein the n-channel MISFET is included in a static random access memory (SRAM).
3. A method of fabricating a semiconductor device according to claim 1 , wherein the p-channel MISFET is included in a dynamic random access memory (DRAM).