Method and system for generating parallel decodable low density parity check (LDPC) codes

1. A method comprising:

decoding, by a plurality of processors operating in parallel, low density parity check (LDPC) codes by accessing a mapped matrix in a memory structure, wherein the mapped matrix is constructed based on a parity check matrix of the LDPC codes,

wherein no two different entries in an identical row of the mapped matrix connect to identical bit nodes or identical check nodes.

2. A method according to claim 1 , further comprising:

if bit node group, BG i , represents all bit nodes connected to edges in an ith row, for i≠j, BG i and BG j , verifying that BG i either has no any common node or is identical; and

if check node group, CG i , represents all the check nodes connected to edges in an ith row, for i≠j, CG i and CG j , verifying that CG i either has no any common node or is identical.

3. A method according to claim 1 , wherein the parity check matrix is permutation equivalent to a block matrix having entries of n×n density balanced matrices.

4. A method according to claim 3 , wherein one of the entries of the n×n density balanced matrices is a m×m density balanced matrix, and other entries of the n×n density balanced matrices are decomposable into block density balanced submatrices.

5. A method according to claim 4 , wherein m is an integer fraction of n.

6. A method according to claim 1 , wherein the LDPC codes are represented by a signal modulated according to a signal constellation that comprises at least one of 8-PSK (Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying).

7. A method according to claim 6 , further comprising operating a transmitter to transmit the signal over a satellite link.

8. A receiver configured to receive a signal representing the LDPC codes in accordance with claim 1 .

9. A method comprising:

generating low density parity check (LDPC) codes by a processor,

wherein the LDPC codes are arranged to be decoded in parallel by a plurality of processors using a mapped matrix that is constructed based on a parity check matrix of the LDPC codes,

wherein no two different entries in an identical row of the mapped matrix connect to identical bit nodes or identical check nodes.

10. A method according to claim 9 , further comprising:

if bit node group, BG i , represents all bit nodes connected to edges in an ith row, for i≠j, BG i and BG j , verifying that BG i either has no any common node or is identical; and

if check node group, CG i , represents all the check nodes connected to edges in an ith row, for i≠j, CG i and CG j , verifying that CG i either has no any common node or is identical.

11. A method according to claim 9 , wherein the parity check matrix is permutation equivalent to a block matrix having entries of n×n density balanced matrices.

12. A method according to claim 11 , wherein one of the entries of the n×n density balanced matrices is a m×m density balanced matrix, and other entries of the n×n density balanced matrices are decomposable into block density balanced submatrices.

13. A method according to claim 12 , wherein m is an integer fraction of n.

14. A method according to claim 9 , wherein the LDPC codes are represented by a signal modulated according to a signal constellation that comprises at least one of 8-PSK (Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying).

15. A method according to claim 14 , wherein the signal is transmitted over a satellite link.

16. A transmitter configured to transmit a signal representing the LDPC codes in accordance with claim 9 .

17. An apparatus comprising:

logic configured to determine that none of any two different entries in an identical row of a mapped matrix connects to identical bit nodes or identical check nodes, wherein the mapped matrix is based on a parity check matrix corresponding to low density parity check (LDPC) codes, the mapped matrix being stored into memory that is accessible by a plurality of processors operating in parallel to decode the LDPC codes,

wherein the logic is further configured, if bit node group, BG i , represents all bit nodes connected to edges in an ith row, for i≠j, BG i and BG j , to verify that BG i either has no any common node or is identical,

wherein the logic is further configured, if check node group, CG i , represents all the check nodes connected to edges in an ith row, for i≠j, CG i and CG j , to verify that CG i either has no any common node or is identical.

18. An apparatus according to claim 17 , wherein the number of processors is n, the logic being further configured to delete edge values within the mapped matrix to output a derived mapped matrix, wherein the derived mapped matrix is used by m parallel processors, m being less than n.

19. An apparatus comprising:

a memory structure comprising a mapped matrix that is based on a parity check matrix of low density parity check (LDPC) codes, wherein no two different entries in an identical row of the mapped matrix connect to identical bit nodes or identical check nodes; and

a plurality of processors configured to operate in parallel accessing the mapped matrix to decode the LDPC codes.

20. The apparatus of claim 19 , wherein the parity check matrix is permutation equivalent to a block matrix having entries of n×n density balanced matrices.

21. The apparatus of claim 20 , wherein one of the entries of the n×n density balanced matrices is a m×m density balanced matrix, and other entries of the n×n density balanced matrices are decomposable into block density balanced submatrices.

22. The apparatus of claim 21 , wherein m is an integer fraction of n.

23. The apparatus of claim 19 , wherein the LDPC codes are represented by a signal modulated according to a signal constellation that comprises at least one of 8-PSK (Phase Shift Keying) or QPSK (Quadrature Phase Shift Keying).

24. The apparatus of claim 23 , further comprising a transmitter configured to transmit the signal over a communication link.