System for and method of capturing application characteristics data from a computer system and modeling target system
View Patent ↗A system for, method of and computer program product captures performance-characteristic data from the execution of a program and models system performance based on that data. Performance-characterization data based on easily captured reuse distance metrics is targeted, defined as the total number of memory references between two accesses to the same piece of data. Methods for efficiently capturing this kind of metrics are described. These data can be refined into easily interpreted performance metrics, such as performance data related to caches with LRU replacement and random replacement strategies in combination with fully associative as well as limited associativity cache organizations. Methods for assessing cache utilization as well as parallel execution are covered.
1. A method, comprising:
executing a sequence of operations for a plurality of threads of a multithreaded program of instructions in response to said program of instructions;
selecting a set of operations from said sequences of operations;
monitoring respective operations of said set of operations in response to a first thread from the plurality of threads;
recording access information associated with respective operations of said set of operations and identifying one or more memory objects being accessed by respective ones of said set of operations;
enabling a trap mechanism operable to detect one or more next operations accessing one or more of said memory objects in response to a second thread, different from the first thread, from the plurality of threads, access information associated with the second thread being stored in performance characteristic data, the trap mechanism remaining active until an operation from the first thread triggers a watch point mechanism; and
recording access information about said next operations.
2. The method according to claim 1 , wherein only a limited number of trap mechanisms from the plurality of threads different than from the first thread being recorded.
3. The method according to claim 1 , wherein a write operation from the one or more next operations is an indicator for a communication miss.
4. A method, comprising:
executing a sequence of operations for a plurality of threads of a multithreaded program of instructions in response to a program of instructions;
selecting a set of operations from said sequences of operations;
monitoring respective operations of said set of operations in response to a first thread from the plurality of threads;
recording, when at least one of the respective operations is a write operation, access information associated with respective operations of said set of operations and identifying one or more memory objects being accessed by respective ones of said set of operations;
enabling a trap mechanism operable to detect one or more next operations accessing one or more of said memory objects in response to a second thread, different from the first thread, from the plurality of threads, access information associated with the second thread being stored in performance characteristic data, the trap mechanism remaining active until an operation from the first thread triggers a watch point mechanism;
recording access information about said next operations; and
indicating a communication miss when at least one of the one or more next operations is a write operation.
5. A method, comprising:
executing a sequence of operations for a plurality of threads of a multithreaded program of instructions in response to a program of instructions;
selecting a set of operations from said sequences of operations;
monitoring respective operations of said set of operations in response to a first thread from the plurality of threads;
recording, when at least one of the respective operations is a write operation, access information associated with respective operations of said set of operations and identifying one or more memory objects being accessed by respective ones of said set of operations;
enabling a trap mechanism operable to detect one or more next operations accessing one or more of said memory objects in response to a second thread, different from the first thread, from the plurality of threads, access information associated with the second thread being stored in performance characteristic data;
recording access information about said next operations and an identity within said memory objects being accesses by each thread; and
indicating a false sharing miss when the first thread does not access a same data as the second thread,
trap mechanism remaining active until an operation from the first thread triggers a watch point mechanism, only a limited number of trap mechanisms from plurality of threads different than from the first thread being recorded.
6. A method, comprising of:
executing a sequence of operations for a plurality of threads of a multithreaded program of instructions in response to a program of instructions;
selecting a set of operations from said sequences of operations;
monitoring respective operations of said set of operations in response to a first thread from the plurality of threads;
recording, when at least one of the respective operations is a write operation, access information associated with respective operations of said set of operations and identifying one or more memory objects being accessed by respective ones of said set of operations;
enabling a trap mechanism operable to detect one or more next operations accessing one or more of said memory objects in response to a second thread, different from the first thread, from the plurality of threads, access information associated with the second thread being stored in performance characteristic data;
recording access information about said next operations; and
indicating a communication miss when at least one of the one or more next operations is a write operation,
the trap mechanism remaining active until an operation from the first thread triggers a watch point mechanism, only a limited number of trap mechanisms from the plurality of threads different than from the first thread being recorded.
7. A method, comprising:
gathering memory usage information from an execution of a program of instructions for at least two memory object sizes;
estimating an amount of communication misses for each of said memory object sizes; and
estimating a false sharing responsive to a number of communication misses detected for a specific instruction for a memory object satisfying a predetermined memory object size criteria, the estimating excluding each memory object having a memory object size smaller than said predetermined memory object size criteria.
8. A method, comprising;
gathering memory usage information from an execution of a program of instructions for at least two memory object sizes;
estimating an amount of communication misses for each of said memory object sizes to define an estimated amount of communication misses; and
estimating a communication efficiency based on a ratio between the estimated amount of communication misses for said two memory object sizes, the estimating excluding each memory object having a smaller object size memory than a predetermined memory object size criteria.