IP Library Granted Patent US 7,521,997
Granted Patent B2
US 7,521,997 · App. 11/938,363 · Granted Apr 21, 2009

Low-power variable gain amplifier

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Quick Facts
Patent No.
US 7,521,997
App. No.
11/938,363
Granted
Apr 21, 2009
Kind
B2
Abstract

Provided is a low-power variable gain amplifier having a direct-current (DC) bias stabilizer. The low-power variable gain amplifier includes: a load block through which first and second load currents flow from a first source voltage; a first differential input signal source including a terminal connected to a second source voltage and the other terminal connected to a variable gain amplifying block and sinking currents corresponding to a value of a first differential input current signal; a second differential input signal source including a terminal connected to the second source voltage and the other terminal connected to the variable gain amplifying block and sinking currents corresponding to a value of a second differential input current signal; a variable gain amplifying block sinking first and second differential output current signals that are branch currents of the first and load currents, respectively, and first and second destructive-compensation current signals, in response to first and second gain control signals and the first and second differential input current signals; and the DC bias stabilizer processing the first and second destructive-compensation current signals and first and second bias currents that are branch currents of the first and second load currents, respectively, to enable the first and second load currents to include fixed DC current components, wherein the currents sunk to the first and second differential input signal sources include DC current components and AC current components, the DC current components of the first and second differential input signal sources have the same value, and the AC current components thereof have a phase difference of 180°.

Claims (34)

1. A low-power variable gain amplifier comprising:

a load block through which first and second load currents flow from a first source voltage;

a first differential input signal source including a terminal connected to a second source voltage and the other terminal connected to a variable gain amplifying block and sinking currents corresponding to a value of a first differential input current signal;

a second differential input signal source including a terminal connected to the second source voltage and the other terminal connected to the variable gain amplifying block and sinking currents corresponding to a value of a second differential input current signal;

a variable gain amplifying block sinking first and second differential output current signals that are branch currents of the first and second load currents, respectively, and first and second destructive-compensation current signals, in response to first and second gain control signals and the first and second differential input current signals; and

a DC (direct-current) bias stabilizer processing the first and second destructive-compensation current signals and first and second bias currents that are branch currents of the first and second load currents, respectively, to enable the first and second load currents to include fixed DC current components,

wherein the currents sunk to the first and second differential input signal sources include DC current components and AC current components, the DC current components of the first and second differential input signal sources have the same value, and the AC current components thereof have a phase difference of 180°.

2. The low-power variable gain amplifier of claim 1 , wherein the variable gain amplifying block comprises:

a first bipolar transistor including a terminal sinking the first differential output current signal, the other terminal connected to the other terminal of the first differential input signal source, and a base terminal applied with the first gain control signal;

a second bipolar transistor including a terminal sinking the first destructive-compensation current signal, the other terminal connected to the other terminal of the first differential input signal source, and a base terminal applied with the second gain control signal;

a third bipolar transistor including a terminal sinking the first destructive-compensation current signal, the other terminal connected to the other terminal of the second differential input signal source, and a base terminal applied with the second gain control signal; and

a fourth bipolar transistor including a terminal sinking the second differential output current signal, the other terminal connected to the other terminal of the second differential input signal source, and a base terminal applied with the first gain control signal.

3. The low-power variable gain amplifier of claim 1 , wherein the variable gain amplifying block comprises:

a first MOS (metal-oxide-semiconductor) transistor including a terminal sinking the first differential output current signal, the other terminal connected to the other terminal of the first differential input signal source, and a gate terminal applied with the first gain control signal;

a second MOS transistor including a terminal sinking the first destructive-compensation current signal, the other terminal connected to the other terminal of the first differential input signal source, and a gate terminal applied with the second gain control signal,

a third MOS transistor including a terminal sinking the first destructive-compensation current signal, the other terminal connected to the other terminal of the second differential input signal source, and a gate terminal applied with the second gain control signal; and

a fourth MOS transistor including a terminal sinking the second differential output current signal, the other terminal connected to the other terminal of the second differential input signal source, and a gate terminal applied with the first gain control signal.

4. The low-power variable gain amplifier of claim 1 ,

wherein the DC bias stabilizer comprises:

a first bias resistor including a terminal connected to a node through which the first bias current flows and the other terminal through which the first destructive-compensation current signal flows; and

a second bias resistor including a terminal connected to a node through which the second bias current flows and the other terminal through which the second destructive-compensation current signal flows, and

wherein the node through which the first destructive-compensation current signal flows and the node through which the second destructive-compensation current signal flows are connected to each other.

5. The low-power variable gain amplifier of claim 1 ,

wherein the DC bias stabilizer comprises:

a first bias bipolar transistor including a terminal connected to a node through which the first bias current flows, the other terminal through which the first destructive-compensation current signal flows, and a base terminal applied with a bias voltage; and

a second bias bipolar transistor including a terminal connected to a node through which the second bias current flows, the other terminal through which the second destructive-compensation current signal flows, and a base terminal applied with the bias voltage, and

wherein the node through which the first destructive-compensation current signal flows and the node through which the second destructive-compensation current signal flows are connected to each other.

6. The low-power variable gain amplifier of claim 5 , wherein the DC bias stabilizer further comprises a bias generator generating the bias voltage.

7. The low-power variable gain amplifier of claim 5 ,

wherein the DC bias stabilizer comprises:

a first bias MOS transistor including a terminal connected to a node through which the first bias current flows, the other terminal connected to a node through which the first destructive-compensation current signal flows, and a gate terminal applied with a bias voltage; and

a second bias MOS transistor including a terminal connected to a node through which the second bias current flows, the other terminal connected to a node through which the second destructive-compensation current signal flows, and a gate terminal applied with the bias voltage, and

wherein the node through which the first destructive-compensation current signal flows and the node through which the second destructive-compensation current signal flows are connected to each other.

8. The low-power variable gain amplifier of claim 5 , wherein the DC bias stabilizer further comprises a bias generator generating the bias voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: FCI INC.
To: DIALOG SEMICONDUCTOR KOREA INC.
Reel/Frame 053702/0013 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2007
From: BECK, SUNG HO; HWANG, MYUNG WOON
To: FCI INC.
Reel/Frame 020095/0389 →