IP Library › Granted Patent US 7,557,659

Granted Patent B2

US 7,557,659 · App. 11/940,933 · Granted Jul 7, 2009

Slew-enhanced input stages and amplifiers

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Quick Facts

Patent No.: US 7,557,659
App. No.: 11/940,933
Granted: Jul 7, 2009
Kind: B2

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Abstract

Provided herein are input stages, and operation amplifiers including input stages. In an embodiment, an input stage includes a complimentary differential input transconductor, first and second npn-pnp current mirrors, and first and second pnp-npn current mirrors. The complimentary differential input transconductor includes a pair of differential inputs that accept a pair of voltage signals, a first pair of complimentary differential outputs that output current signals I 1 and I 2 , and a second pair of complimentary differential outputs that output current signals I 3 and I 4 . Each current mirror accepts one of the current signals I 1 , I 2 , I 3 and I 4 , and outputs a pair of current signals (e.g., I 1 ′ and I 1 ″) that are proportional to the accepted current signal (e.g., I 1 ). Current signals I 1 ′ and I 3 ′ are added to produce a first output current (Iout) of the input stage. Current signals I 2 ′ and I 4 ′ are added to produce a second output current (Iout_bar) of the input stage.

Claims (93)

1. An input stage, comprising:

a complimentary differential input transconductor including

a pair of differential inputs that accept a pair of voltage signals;

a first pair of complimentary differential outputs that output current signals I 1 and I 2 ; and

a second pair of complimentary differential outputs that output current signals I 3 and I 4 ;

a first npn-pnp current mirror having an input and a pair of outputs, the input accepting the current signal I 1 , and the pair of outputs outputting current signals I 1 ′ and I 1 ″ that are proportional to the current signal I 1 ;

a second npn-pnp current mirror having an input and a pair of outputs, the input accepting the current signal I 2 , and the pair of outputs outputting current signals I 2 ′ and I 2 ″ that are proportional to the current signal I 2 ;

a first pnp-npn current mirror having an input and a pair of outputs, the input accepting the current signal I 3 , and the pair of outputs outputting current signals I 3 ′ and I 3 ″ that are proportional to the current signal I 3 ; and

a second pnp-npn current mirror having an input and a pair of outputs, the input accepting the current signal I 4 , and the outputs outputting current signals I 4 ′ and I 4 ″ that are proportional to the current signal I 4 ;

wherein the current signals I 1 ′ and I 3 ′ are added to produce a first output current (Iout) of the input stage; and

wherein the current signals I 2 ′ and I 4 ′ are added to produce a second output current (Iout_bar) of the input stage.

2. The input stage of claim 1 , wherein to reduce non-linearities between the npn-pnp current mirrors and the pnp-npn current mirrors:

the current signals I 1 ″ and I 2 ″ output by the first and second npn-pnp current mirrors are provided to the second and first pnp-npn current mirrors; and

the current signals I 3 ″ and I 4 ″ output by the first and second pnp-npn current mirrors are provided to the second and first npn-pnp current mirrors.

3. The input stage of claim 1 , wherein:

the first and second npn-pnp current mirrors each includes a npn emitter-follower transistor having a base that forms the input of the current mirror, a collector connected to a high voltage rail, and an emitter connected to bases of two pnp output transistors, with collectors of the two pnp output transistors forming the pair of outputs of the npn-pnp current mirrors; and

the first and second pnp-npn current mirrors each includes a pnp emitter-follower transistor having a base that forms the input of the current mirror, a collector connected to a low voltage rail, and an emitter connected to bases of two npn output transistors, with collectors of the two npn output transistors forming the pair of outputs of the pnp-npn current mirrors.

4. The input stage of claim 3 , wherein:

the current signal I 1 ″, output by one of the outputs of the first npn-pnp current mirror, is provided to the emitter of the pnp transistor whose base forms the input of the second pnp-npn current mirror;

the current signal I 2 ″, output by one of the outputs of the second npn-pnp current mirror, is provided to the emitter of the pnp transistor whose base forms the input of the first pnp-npn current mirror;

the current signal I 3 ″, output by one of the outputs of the first pnp-npn current mirror, is provided to the emitter of the npn transistor whose base forms the input of the second npn-pnp current mirror; and

the current signal I 4 ″, output by one of the outputs of the second pnp-npn current mirror, is provided to the emitter of the npn transistor whose base forms the input of the first npn-pnp current mirror.

5. The input stage of claim 4 , further comprising:

a first resistor having a first terminal connected to the high voltage rail and having a second terminal;

a second resistor having a first terminal connected to the low voltage rail and having a second terminal;

wherein the first npn-pnp current mirror includes a resistor connected between the second terminal of the first resistor and the base of the npn transistor that forms the input of the first npn-pnp current mirror;

wherein the second npn-pnp current mirror includes a resistor connected between the second terminal of the first resistor and the base of the npn transistor that forms the input of the second npn-pnp current mirror;

wherein the first pnp-npn current mirror includes a resistor connected between the second terminal of the second resistor and the base of the pnp transistor that forms the input of the first pnp-npn current mirror; and

wherein the second pnp-npn current mirror includes a resistor connected between the second terminal of the second resistor and the base of the pnp transistor that forms the input of the second pnp-npn current mirror.

6. The input stage of claim 5 , wherein:

a first common-mode control current is provided to the second terminal of the first resistor to increase in tandem sourcing magnitudes of the first and second output currents (Iout and Iout_bar) of the input stage; and

a second common-mode control current is provided to the second terminal of the second resistor to increase in tandem sinking magnitudes of the first and second output currents (Iout and Iout_bar) of the input stage.

7. The input stage of claim 6 , wherein:

the first and second common-mode control currents are produced by a common-mode transconductance stage that provides the first and second common-mode control currents to the input stage in response to a monitoring of the common-mode voltage, determined based on the first and second output currents (Iout and Iout_bar) of the input stage, to adjust the common-mode voltage to substantially equal a common-mode reference voltage.

8. The input stage of claim 5 , wherein:

a first common-mode control current is provided to the second terminal of the first resistor, and a second common-mode control current is provided to the second terminal of the second resistor, to maintain a common-mode of the first and second output currents (Iout and Iout_bar) at a substantially zero quiescent current.

9. An operation-amplifier, comprising:

an input stage;

a common-mode transconductance stage; and

an output stage;

wherein the input stage comprises:

a complimentary differential input transconductor including

a pair of differential inputs that accept a pair of voltage signals;

a first pair of complimentary differential outputs that output current signals I 1 and I 2 ; and

a second pair of complimentary differential outputs that output current signals I 3 and I 4 ;

wherein the current signals I 1 ′ and I 3 ′ are added to produce a first output current (Iout) of the input stage;

wherein the current signals I 2 ′ and I 4 ′ are added to produce the second output current (Iout_bar) of the input stage;

wherein the output stage receives the first and second output currents (Iout and Iout_bar) of the input stage and based thereon determines a common-mode voltage; and

wherein the common-mode transconductance stage produces and provides first and second common-mode control currents to the input stage to adjust the common-mode voltage to substantially equal the common-mode reference voltage.

10. The operation-amplifier of claim 9 , wherein:

the first common-mode control current is provided to the second terminal of the first resistor to increase in tandem sourcing magnitudes of the first and second output currents (Iout and Iout_bar) of the input stage; and

the second common-mode control current is provided to the second terminal of the second resistor to increase in tandem sinking magnitudes of the first and second output currents (Iout and Iout_bar) of the input stage.

11. The operation-amplifier of claim 10 , wherein:

the current signals I 1 ″ and I 2 ″ output by the first and second npn-pnp current mirrors are provided to the second and first pnp-npn current mirrors; and

the current signals I 3 ″ and I 4 ″ output by the first and second pnp-npn current mirrors are provided to the second and first npn-pnp current mirrors.

12. The operation-amplifier of claim 11 , wherein:

13. The operation-amplifier of claim 12 , wherein:

14. The operation-amplifier of claim 13 , wherein the input stage also comprises:

a first resistor having a first terminal connected to the high voltage rail and having a second terminal; and

a second resistor having a first terminal connected to the low voltage rail and having a second terminal;

wherein the second npn-pnp current mirror includes a resistor) connected between the second terminal of the first resistor and the base of the npn transistor that forms the input of the second npn-pnp current mirror;

15. The operation-amplifier of claim 14 , wherein:

the first common-mode control current is provided to the second terminal of the first resistor; and

the second common-mode control current is provided to the second terminal of the second resistor.

16. A method for producing differential current signals based on a pair of voltage signals, comprising:

accepting a pair of voltage signals and producing therefrom a first pair of complimentary differential output current signals I 1 and I 2 , and a second pair of complimentary differential output current signals I 3 and I 4 ;

producing, based on the current signal I 1 , current signals I 1 ′ and I 1 ″ that are proportional to the current signal I 1 ;

producing, based on the current signal I 2 , current signals I 2 ′ and I 2 ″ that are proportional to the current signal I 2 ;

producing, based on the current signal I 3 , current signals I 3 ′ and I 3 ″ that are proportional to the current signal I 3 ;

adding the current signals I 1 ′ and I 3 ′ to produce a first output current (Iout); and

adding the current signals I 2 ′ and I 4 ′ to produce a second output current (Iout_bar).

17. The method of claim 16 , further comprising:

increasing in tandem sourcing magnitudes of the first and second output currents (Iout and Iout_bar) in response to a first common-mode control current; and

increasing in tandem sinking magnitudes of the first and second output currents (Iout and Iout_bar) in response to a second common-mode control current.

18. The method of claim 17 , further comprising:

producing, based on the first and second output currents (Iout and Iout_bar), a common-mode voltage; and

adjusting the common-mode voltage to substantially equal a common-mode reference voltage using the first and second common-mode control currents.

19. The method of claim 16 , further comprising:

maintaining a common-mode of the first and second output currents (Iout and Iout_bar) at a substantially zero quiescent current using a first common-mode control current and a second common-mode control current.

Assignments (3)

CHANGE OF NAME Recorded Jun 10, 2014

From: INTERSIL AMERICAS INC.

To: INTERSIL AMERICAS LLC

Reel/Frame 033119/0484 →

SECURITY AGREEMENT Recorded May 4, 2010

From: INTERSIL CORPORATION; TECHWELL, INC.; INTERSIL COMMUNICATIONS, INC.; QUELLAN, INC.; ZILKER LABS, INC.; KENET, INC.; INTERSIL AMERICAS INC.; ELANTEC SEMICONDUCTOR, INC.; D2AUDIO CORPORATION; PLANET ATE, INC.

To: MORGAN STANLEY & CO. INCORPORATED

Reel/Frame 024329/0411 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2007

From: HARVEY, BARRY

To: INTERSIL AMERICAS INC.

Reel/Frame 020124/0152 →