Semiconductor switch circuit having MOS transistors with low current consumption
View Patent ↗A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit 100 has P-type MOS transistors Q 101 and Q 102 for conduction that share a source and are connected in series between an input/output terminal 101 and input/output terminal 102 , a P-type MOS transistor Q 103 and N-type MOS transistor Q 105 having drains connected to the gate of Q 101 , a P-type MOS transistor Q 104 and N-type MOS transistor Q 106 having drains connected to the gate of Q 102 , and a control terminal 103 connected to the gates of the transistors. Further semiconductor switch circuit 100 is configured with the sources and back gates of Q 103 and Q 104 connected to the sources of Q 101 and Q 102 . Therefore, it is possible to switch the path between input/output terminal 101 and input/output terminal 102 between a conduction state and non-conduction state by means of voltage control by voltage value Vcont of a control signal applied to control terminal 103.
1. A semiconductor switch circuit comprising:
first and second MOS transistors for conduction that share a source and are connected in series between a first input/output terminal and second input/output terminal;
third and fifth MOS transistors having drains connected to a gate of said first MOS transistor;
fourth and sixth MOS transistors having drains connected to a gate of said second MOS transistor; and
a control terminal connected, via a common connection, to gates of said third through sixth MOS transistors, wherein:
sources and back gates of said third and fourth MOS transistors have a common connection to sources of said first and second MOS transistors; and
said gate of said first MOS transistor and said gate of said second MOS transistor are configured for individual control.
2. The semiconductor switch circuit according to claim 1 , wherein sources of said third and fourth MOS transistors are connected to sources of said first and second MOS transistors via a resistance.
3. The semiconductor switch circuit according to claim 1 , wherein:
said first through fourth MOS transistors are configured with P-type MOS transistors;
said fifth and sixth MOS transistors are configured with N-type MOS transistors; and
a conduction state is established between said first input/output terminal and said second input/output terminal by applying a positive voltage to said control terminal.
4. The semiconductor switch circuit according to claim 1 , wherein:
said first through fourth MOS transistors are configured with N-type MOS transistors;
said fifth and sixth MOS transistors are configured with P-type MOS transistors; and
a conduction state is established between said first input/output terminal and said second input/output terminal by applying a negative voltage to said control terminal.
5. A semiconductor switch circuit comprising:
first and second MOS transistors for conduction that share a source and are connected in series between a first input/output terminal and second input/output terminal;
third and fourth MOS transistors configuring a source follower that controls a gate potential of said first and second MOS transistors;
fifth and sixth MOS transistors that control a gate potential of said third and fourth MOS transistors; and
a control terminal connected, via a common connection, to gates of said third through sixth MOS transistors, wherein:
drains of said third and fifth MOS transistors are connected to a gate of said first MOS transistor;
drains of said fourth and sixth MOS transistors are connected to a gate of said second MOS transistor;
sources and back gates of said third and fourth MOS transistors have a common connection to sources of said first and second MOS transistors; and
said gate of said first MOS transistor and said gate of said second MOS transistor are configured for individual control.