IP Library Granted Patent US 7,829,442
Granted Patent B2
US 7,829,442 · App. 11/941,629 · Granted Nov 9, 2010

Semiconductor heterostructures having reduced dislocation pile-ups and related methods

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 7,829,442
App. No.
11/941,629
Granted
Nov 9, 2010
Kind
B2
Abstract

Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Claims (26)

1. A method for forming a semiconductor structure, the method comprising the steps of:

epitaxially growing over a substrate a relaxed graded layer comprising a III-V compound, the III-V compound comprising a group III element and a group V element; and

epitaxially growing a compositionally uniform cap layer comprising the group III element and the group V element over the relaxed graded layer,

wherein (i) a concentration of the group III element in the relaxed graded layer increases at a grading rate exceeding about 25% per micrometer, (ii) a threading dislocation density of the compositionally uniform cap layer is less than approximately 10 7 /cm 2 , and (iii) the group V element comprises phosphorous.

2. The method of claim 1 , wherein the group III element comprises indium.

3. The method of claim 1 , wherein the group III element comprises gallium.

4. The method of claim 1 , wherein the relaxed graded layer further comprises arsenic.

5. The method of claim 1 , wherein the group III element comprises indium, the relaxed graded layer further comprises arsenic, and the relaxed graded layer further comprises gallium.

6. The method of claim 1 , further comprising epitaxially growing at least one strained layer comprising a III-V compound over the compositionally uniform cap layer.

7. The method of claim 1 , further comprising:

bonding the semiconductor structure to a handle wafer; and

removing at least the substrate.

8. The method of claim 1 , wherein the compositionally uniform cap layer has a dislocation pile-up density less than approximately 1/cm.

9. The method of claim 1 , wherein the relaxed graded layer comprises at least two regions having different local grading rates.

10. The method of claim 1 , wherein the threading dislocation density of the compositionally uniform cap layer is less than approximately 5×10 5 /cm 2 .

11. A method for forming a semiconductor structure, the method comprising the steps of:

epitaxially growing over a substrate a relaxed graded layer comprising a III-V compound, the III-V compound comprising a group III element and a group V element; and

epitaxially growing a compositionally uniform cap layer comprising the group III element and the group V element over the relaxed graded layer,

wherein (i) a concentration of the group III element in the relaxed graded layer increases at a grading rate exceeding about 25% per micrometer, (ii) a threading dislocation density of the compositionally uniform cap layer is less than approximately 10 7 /cm 2 , (iii) the group III element comprises indium, (iv) the group V element comprises phosphorous, and (v) the relaxed graded layer further comprises gallium.

12. The method of claim 11 , further comprising epitaxially growing at least one strained layer comprising a III-V compound over the compositionally uniform cap layer.

13. The method of claim 11 , further comprising:

bonding the semiconductor structure to a handle wafer; and

removing at least the substrate.

14. The method of claim 11 , wherein the compositionally uniform cap layer has a dislocation pile-up density less than approximately 1/cm.

15. The method of claim 11 , wherein the relaxed graded layer comprises at least two regions having different local grading rates.

16. The method of claim 11 , wherein the threading dislocation density of the compositionally uniform cap layer is less than approximately 5×10 5 /cm 2 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: AMBERWAVE SYSTEMS CORPORATION
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 023775/0111 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2008
From: LEITZ, CHRISTOPHER; VINEIS, CHRISTOPHER; WESTHOFF, RICHARD; YANG, VICKY; CURRIE, MATTHEW
To: AMBERWAVE SYSTEMS CORPORATION
Reel/Frame 020526/0901 →
Continuity (3)
Continuation 1064635300 · Aug 22, 2003
Provisional Application 6040548400 · Aug 23, 2002
Related Publication 20080079024A1 · Apr 3, 2008