Pre-processing data samples from parallelized data converters
View Patent ↗An apparatus for pre-processing data samples from parallelized analog-to-digital converters (ADC). An ADC converts an analog signal into N parallel digital data samples that are output on N ADC links x 0 through x N-1 . A parallel computation block in communication with the ADC processes the data samples in parallel prior to storage into a memory.
1. An apparatus, comprising:
an analog-to-digital converter (ADC) that converts an analog signal into N parallel digital data samples output on N ADC links x 0 through x N-1 ; and
a parallel computation block in communication with the ADC that processes the data samples in parallel prior to storage into a memory,
wherein the parallel computation block divides a computation into N related and substantially similar sub-computations performed by N sub-blocks, each sub-block receiving at least one of the N ADC links as input, each sub-block processing the data samples received at its input in cooperation with the other sub-blocks to collectively generate a solution to the computation.
2. An apparatus as in claim 1 , without a memory controller between the ADC and the parallel computation block.
3. An apparatus as in claim 2 , without a memory between the ADC and the parallel computation block.
4. An apparatus as in claim 1 , wherein the parallel computation block is implemented with at least one device selected from the group consisting of: field programmable gate arrays (FPGAs), programmable logic devices (PLDs), application specific integrated circuits (ASICs), digital signal processors (DSPs), and microprocessors.
5. An apparatus as in claim 4 , wherein each sub-block is implemented with its own dedicated device.
6. An apparatus as in claim 1 , further comprising:
a memory that stores the output of the parallel computation block.
7. An apparatus as in claim 1 , wherein the parallel computation block computes a partial Fourier Transform on the data samples.
8. An apparatus as in claim 1 , wherein the parallel computation block is a Finite Impulse Response (FIR) filter.
9. An apparatus as in claim 8 , wherein each of the N sub-blocks includes at least one delay element.
10. An apparatus as in claim 9 , wherein the N ADC links are identified as ADC links x 0 through x N-1 , and the (N−1) th sub-block receives ADC link x 0 as input.
11. An apparatus as in claim 10 , wherein the FIR filter computes
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12. An apparatus as in claim 1 , wherein the parallel computation block is an Infinite Impulse Response (IIR) filter.
13. An apparatus as in claim 1 , wherein the apparatus is a measurement instrument.
14. An apparatus, comprising:
an analog-to-digital converter (ADC) that converts an analog signal into N parallel digital data samples output on N ADC links x 0 through x N-1 ; and
a parallel computation block in communication with the ADC that processes the data samples in parallel prior to storage into a memory,
wherein the parallel computation block further comprises N sub-blocks, each sub-block receiving at least one of the N ADC links as input, each sub-block processing the data samples received at its input in parallel with the other sub-blocks,
wherein the parallel computation block generates a first histogram from the data samples.
15. An apparatus as in claim 14 , wherein each of the N sub-blocks generates sub-histograms on the data samples received on its ADC link.
16. An apparatus as in claim 15 , wherein the parallel computation block combines the sub-histograms generated from the N sub-blocks to generate the first histogram.
17. An apparatus, comprising:
an analog-to-digital converter (ADC) that converts an analog signal into N parallel digital data samples output on N ADC links x 0 through x N-1 ; and
a parallel computation block in communication with the ADC that processes the data samples in parallel prior to storage into a memory,
wherein the parallel computation block further comprises N sub-blocks, each sub-block receiving at least one of the N ADC links as input, each sub-block processing the data samples received at its input in parallel with the other sub-blocks,
wherein each of the N sub-blocks compute inner Fourier Transforms on the data samples received on its ADC link, and
wherein the inner Fourier Transform includes a calculation of the expression
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further comprising:
n 1 Z-calculators that determine
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for each k 1 from 0 to n 1 −1 and for each j 2 from 0 to n 2 −1.
18. An apparatus as in claim 17 , further comprising:
a memory that stores the inner Fourier Transforms; and
a processor that computes outer Fourier Transforms on the inner Fourier Transforms stored in the memory.
19. An apparatus, comprising:
an analog-to-digital converter (ADC) that converts an analog signal into N parallel digital data samples output on N ADC links x 0 through x N-1 ; and
a parallel computation block in communication with the ADC that processes the data samples in parallel prior to storage into a memory,
wherein the parallel computation block further comprises N sub-blocks, each sub-block receiving at least one of the N ADC links as input, each sub-block processing the data samples received at its input in parallel with the other sub-blocks,
wherein the parallel computation block is a time-dependent filter.
20. An apparatus as in claim 19 , wherein each of the N sub-blocks includes a multiplier that multiplies data samples received on its ADC link by a time-dependent function.