Liquid crystal display device having light blocking line disposed on same layer as gate line
View Patent ↗Active matrix display devices having improved opening and contrast ratios utilize light blocking lines to improve display contrast ratios yet position the light blocking lines on the same level of metallization as the gate lines to thereby limit parasitic capacitive coupling between the data lines and the pixel electrodes. The light blocking lines are also positioned on only one side of the data lines so that improvements in the display's opening ratio can also be achieved. The light blocking lines are preferably patterned so that no overlap occurs between a display's data lines and the light blocking lines. The elimination of overlap reduces the step height in the display's pixel electrodes and thereby reduces the extent of disclination of the liquid crystal molecules in the liquid crystal material extending opposite the pixel electrodes. The light blocking lines are also preferably patterned beneath the display's data lines so that parasitic capacitive coupling between the data lines and the pixel electrodes is reduced. The light blocking lines are also preferably formed with beveled edges so that the step height in the display's pixel electrodes can be reduced even further.
1. A liquid crystal display device, comprising:
a first substrate;
a plurality of gate lines formed on the first substrate;
a plurality of storage lines formed on the first substrate and substantially parallel to the plurality of gate lines;
a plurality of connecting lines formed on the first substrate;
a plurality of data lines electrically insulated from the gate lines, the storage lines and the connecting lines, each of the data lines having a disinclination region;
a pixel electrode overlapping the adjacent data lines and one of the adjacent gate lines;
a second substrate facing the first substrate; and
a liquid crystal layer interposed between the first substrate and the second substrate, and comprising liquid crystal molecules,
wherein a pixel region is districted by the adjacent gate lines and the adjacent data lines, and
one of the plurality of connecting lines is disposed in the pixel region so as to substantially occupy the disinclination region of at least one of the adjacent data lines.
2. The display device of claim 1 , wherein the plurality of data lines and the plurality of connecting lines are not electrically connected.
3. The display device of claim 1 , wherein the plurality of connecting lines are substantially parallel to the plurality of data lines.
4. The display device of claim 1 , further comprising a first insulating layer formed on the plurality of gate lines, the plurality of storage lines and the plurality of connecting lines,
wherein the plurality of data lines are formed on the first insulating layer.
5. The display device of claim 1 , further comprising a second insulating layer formed on the plurality of the data lines,
wherein the pixel electrode is formed on the second insulating layer.
6. The display device of claim 5 , wherein the second insulating layer comprises an organic passivation layer.
7. The display device of claim 4 , wherein the plurality of the gate lines comprises a plurality of gate electrodes formed in pixel regions, and
the plurality of the data lines comprises a plurality of data electrodes formed in pixel regions, and
further comprising a plurality of drain electrodes located against the plurality of source electrodes, and electrically connected to the pixel electrodes.
8. The display device of claim 1 , wherein the plurality of the gate lines, the plurality of storage lines and the plurality of connecting lines have a ladder shape.