Integrated circuit having dielectric layer including nanocrystals

1. An integrated circuit comprising:

a first electrode;

resistivity changing material coupled to the first electrode;

a second electrode; and

a dielectric material layer between the resistivity changing material and the second electrode, the dielectric material layer comprising nanocrystals.

2. The integrated circuit of claim 1 , wherein a current path is formed through the dielectric material layer via the nanocrystals and dielectric breakdown.

3. The integrated circuit of claim 1 , wherein the first electrode, the resistivity changing material, the second electrode, and the dielectric material layer provide a via memory element.

4. The integrated circuit of claim 1 , wherein the first electrode, the resistivity changing material, the second electrode, and the dielectric material layer provide a mushroom memory element.

5. The integrated circuit of claim 1 , wherein the dielectric material layer comprises an oxide material.

6. The integrated circuit of claim 1 , wherein the nanocrystals are located only in a portion of the dielectric material layer aligned with the resistivity changing material.

7. The integrated circuit of claim 1 , wherein the resistivity changing material comprises a phase change material.

8. The integrated circuit of claim 1 , wherein the resistivity changing material comprises a first portion having a first cross-sectional width and a second portion having a second cross-sectional width different from the first cross-sectional width.

9. The integrated circuit of claim 1 , wherein a cross-sectional width of the dielectric material layer is greater than a cross-sectional width of the resistivity changing material.

10. A system comprising:

a host; and

a memory device communicatively coupled to the host, the memory device comprising:

a first electrode;

a dielectric material layer including nanocrystals;

phase change material between the first electrode and the dielectric material layer; and

a second electrode coupled to the dielectric material layer.

11. The system of claim 10 , wherein the memory device further comprises a bit line coupled to the first electrode and an access device coupled to the second electrode.

12. The system of claim 10 , wherein a current path is provided through the dielectric material layer via the nanocrystals and dielectric breakdown.

13. The system of claim 10 , wherein the dielectric material layer has a thickness within a range of 3-15 nanometers.

14. The system of claim 10 , wherein the nanocrystals are implanted in the dielectric material layer.

15. The system of claim 10 , wherein the nanocrystals are grown in the dielectric material layer.

16. The system of claim 10 , wherein the phase change material comprises a first portion having a first cross-sectional width and a second portion having a second cross-sectional width different from the first cross-sectional width.

17. The system of claim 10 , wherein a cross-sectional width of the dielectric material layer is greater than a cross-sectional width of the phase change material.

18. A memory comprising:

a first electrode;

phase change material contacting the first electrode;

an oxide layer including nanocrystals, the oxide layer contacting the phase change material; and

a second electrode contacting the oxide layer.

19. The memory of claim 18 , wherein the nanocrystals are implanted in the oxide layer.

20. The memory of claim 18 , wherein the nanocrystals are grown in the oxide layer.

21. The memory of claim 18 , further comprising:

a bit line coupled to the first electrode; and

an access device coupled to the second electrode.

22. The memory of claim 18 , wherein the phase change material comprises a first portion having a first cross-sectional width and a second portion having a second cross-sectional width different from the first cross-sectional width.

23. The memory of claim 18 , wherein a cross-sectional width of the oxide layer is greater than a cross-sectional width of the phase change material.