Semiconductor device and method of manufacturing the same
View Patent ↗The semiconductor device includes a first MIS transistor including a gate insulating film 92 , a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154 , a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92 , a gate electrode 108 formed on the gate insulating film 96 , source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154 , a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
1. A semiconductor device comprising:
a first MIS transistor formed over a semiconductor substrate and including a first gate insulating film, a first gate electrode formed on the first gate insulating film and first source/drain regions formed in the semiconductor substrate;
a second MIS transistor formed over the semiconductor substrate and including a second gate insulating film thicker than the first gate insulating film, a second gate electrode formed on the second gate insulating film, second source/drain regions formed in the semiconductor substrate and a ballast resistor formed in the semiconductor substrate and connected to one of the second source/drain regions;
a salicide block insulating film formed over the ballast resistor with an insulating film thinner than the second gate insulating film interposed therebetween; and
a silicide film formed on the first source/drain regions and on the second source/drain regions,
wherein an impurity concentration of the ballast resistor is higher than an impurity concentration of LDD regions or extension regions of the second source/drain regions.
2. The semiconductor device according to claim 1 , wherein
the first source/drain regions include a first impurity doped layer formed in alignment with the first gate electrode,
the second source/drain regions include a second impurity doped layer formed in alignment with the second gate electrode, and
the ballast resistor is formed of a third impurity doped layer formed concurrently with the first impurity doped layer, and a fourth impurity doped layer formed concurrently with the second impurity doped layer.
3. The semiconductor device according to claim 2 , wherein
the first impurity doped layer is LDD regions or extension regions of the first source/drain regions, and
the second impurity doped layer is the LDD regions or the extension regions of the second source/drain regions.
4. The semiconductor device according to claim 1 ,
further comprising: a sidewall spacer formed on a side wall of the first gate electrode,
a film thickness of the insulating film being the same as a film thickness of the first gate insulating film formed below the sidewall spacer.
5. The semiconductor device according to claim 1 , wherein
a film thickness of the insulating film is not more than a film thickness of the first gate insulating film.
6. The semiconductor device according to claim 5 , wherein
the first source/drain regions include a first impurity doped layer formed in alignment with the first gate electrode,
the second source/drain regions include a second impurity doped layer formed in alignment with the second gate electrode, and
the ballast resistor is formed of a third impurity doped layer formed concurrently with the first impurity doped layer, and a fourth impurity doped layer formed concurrently with the second impurity doped layer.
7. The semiconductor device according to claim 6 , wherein
the first impurity doped layer is LDD regions or extension regions of the first source/drain regions, and
the second impurity doped layer is the LDD regions or the extension regions of the second source/drain regions.
8. The semiconductor device according to claim 5 ,
further comprising: a sidewall spacer formed on a side wall of the first gate electrode,
a film thickness of the insulating film being the same as a film thickness of the first gate insulating film formed below the sidewall spacer.