Thin film transistor array panel and method for manufacturing the same
View Patent ↗The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.
1. A thin film transistor array panel, comprising:
an insulating substrate;
a gate line formed on the insulating substrate and having a first layer of an aluminum (Al) containing metal and a second layer of a Mo-alloy comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti), the gate line having a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor formed on the gate insulating layer;
a data line formed on the semiconductor, the data line having a source electrode;
a drain electrode formed on the semiconductor, the drain electrode facing the source electrode with a predetermined gap;
a passivation layer formed on the data line and the drain electrode, the passivation layer having a contact hole; and,
a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole,
wherein the data line and the drain electrode have a third layer of a Mo containing metal, a fourth layer of an Al containing metal, and a fifth layer of a Mo containing metal, and at least one of the third and fifth layers comprising a Mo-alloy including molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti),
wherein the semiconductor has the same planar pattern as the data line and the drain electrode except an area between the source electrode and the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein the first layer includes Al-Nd.
3. The thin film transistor array panel of claim 1 , wherein the fourth layer includes Al-Nd.
4. The thin film transistor array panel of claim 1 , wherein the Mo-alloy includes 0.1 to 10 at % of additives Nb, V, and Ti.
5. The thin film transistor array panel of claim 4 , wherein the Mo-alloy includes 3 to 8 at % of the additives Nb, V, and Ti.
6. The thin film transistor array panel of claim 4 , wherein the gate line includes Al-Nd.
7. A thin film transistor array panel, comprising:
an insulating substrate;
a gate line formed on the gate insulating substrate and having a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor formed on the gate insulating layer;
a data line formed on the semiconductor, the data line having a source electrode;
a drain electrode formed on the semiconductor, the drain electrode facing the source electrode with a predetermined gap;
a passivation layer formed on the data line and the drain electrode, the passivation layer having a contact hole; and,
a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole,
wherein the data line and the drain electrode have a first layer of a Mo containing metal, a second layer of an Al containing metal, and a third layer of a Mo containing metal, and at least one of the first and third layers comprising a Mo-alloy including molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti),
wherein the semiconductor has the same planar pattern as the data line and the drain electrode except an area between the source electrode and the drain electrode.
8. The thin film transistor array panel of claim 7 , further comprising a color filter formed under the pixel electrode.
9. The thin film transistor array panel of claim 7 , wherein the gate line includes an Al containing metal.
10. The thin film transistor array panel of claim 9 , wherein the pixel electrode includes one of indium tin oxide (ITO) and indium zinc oxide (IZO).
11. The thin film transistor array panel of claim 7 , wherein the Mo-alloy includes 0.1 to 10 at % of additives Nb, V, and Ti.
12. The thin film transistor array panel of claim 11 , wherein the Mo-alloy includes 3 to 8 at % of the additives Nb, V, and Ti.