IP Library Granted Patent US 7,598,511
Granted Patent B2
US 7,598,511 · App. 11/944,532 · Granted Oct 6, 2009

Energy saving driving circuit and associated method for a solid state relay

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Quick Facts
Patent No.
US 7,598,511
App. No.
11/944,532
Granted
Oct 6, 2009
Kind
B2
Abstract

An energy saving driving circuit and method is provided for use with a solid state relay (SSR). The circuit and method reduce the overall energy required to drive a solid state relay by maintaining the SSR in an “on” state with a minimal maintenance or holding current after applying a turn-n current. The driving circuit includes a control circuit configured for outputting a control signal; a turn-on circuit configured for providing an output current at a first current level for a first time period in response to the control signal; and a holding circuit configured for maintaining said output current at a second reduced current level for a second time period. The maintenance or holding current is reduced in respect of that of a conventional driving current, and in some cases may be an order of magnitude or more less in magnitude than a conventional driving currents thereby resulting in less energy consumed by the SSR.

Claims (25)

1. A solid state relay, comprising:

a relay circuit having a maximum turn-on time and comprising a switch, the relay circuit being configured to operate in an on state when the switch is in a first position and to operate in an off state when the switch is in a second position;

an LED;

an energy-conserving circuit operably connected to, and configured to drive, the LED, comprising:

a control circuit configured to output a control signal in response to receiving an input signal, the output signal causing the switch to assume the first position and thereby cause the relay circuit to operate in the on state;

a turn-on circuit comprising a first resistor and configured to provide a first output current at a first current level to the relay circuit for a first time period in response to the control signal causing the relay circuit to operate in the on state; and

a holding circuit comprising a second resistor and configured to maintain the output current at a reduced second current level for a second time period to maintain the relay circuit in the on state;

wherein the first current level is at least ten times greater than the second current level, the first time period is less than the second time period, and the first time period is greater than or equal to the maximum turn-on time.

2. A solid state relay according to claim 1 , wherein the relay circuit and driving circuit are packaged in an integrated circuit (IC).

3. A solid state relay according to claim 1 , wherein the turn-on circuit is one of a current source, a voltage pulse generator, a current pulse generator and a voltage converter.

4. A solid state relay according to claim 1 , wherein the holding circuit is one of a current source, voltage pulse generator, current pulse generator or voltage converter.

5. The solid state relay of claim 1 , wherein the second resistor has a first resistance greater than a second resistance of the second resistor.

6. The solid state relay of claim 1 , wherein the first position is a closed position and the second position is an open position.

7. The solid state relay of claim 1 , wherein the control signal is periodic.

8. The solid state relay of claim 1 , wherein the turn-on circuit is configured to disengage from the energy conserving driving circuit upon termination of the first time period.

9. The solid state relay of claim 1 , wherein said control circuit is configured to disengage the turn-on circuit.

10. The solid state relay of claim 1 , wherein the holding circuit is configured to disengage from the energy conserving driving circuit upon termination of the second time period.

11. The solid state relay of claim 1 , wherein said control circuit is configured to disengage the holding circuit.

12. The solid state relay of claim 1 , wherein a resistance of the turn-on circuit is less than a resistance of the holding circuit.

13. The solid state relay of claim 1 , wherein the control circuit is configured to determine the first time period and the second time period.

14. The solid state relay of claim 1 , wherein the first and second time periods are determined by a charging time of an RC circuit or an RLC circuit.

15. The solid state relay of claim 1 , wherein the control circuit is a device configured electrically to open and close as controlled by an input drive signal.

16. The solid state relay of claim 1 , wherein the turn-on circuit is configured to be activate upon initiation of the first time period and is configured to be de-activated upon termination of the first time period.

17. The solid state relay of claim 1 , wherein the holding circuit is configured to be activated upon initiation of the second time period and is configured to be de-activated upon termination of the second time period.

18. The solid state relay of claim 1 , wherein the first current level ranges between about 3 mA and about 20 mA.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047195 FRAME: 0827. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047924/0571 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0827 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0528 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2007
From: YOUFA, WANG, MR.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 020149/0466 →