Semiconductor device having metal-insulator-metal capacitor and method of fabricating the same

1. An apparatus comprising:

a lower line formed in a semiconductor substrate;

a first interlayer insulating layer formed over the semiconductor substrate, the first interlayer insulating layer having a first conductor and a second conductor electrically connected to the lower line;

a second interlayer insulating layer formed over the first interlayer insulating layer, the second interlayer insulating layer including a first via hole and a second via hole connected to the first conductor and the second conductor, respectively;

a lower electrode line formed in the first via hole, the lower electrode including a first barrier metal layer, a second barrier metal layer, a second copper seed layer, and a copper layer; and

a capacitor formed in the second via hole, the capacitor including the first barrier metal layer, a dielectric layer, the second barrier metal layer and the second copper seed layer.

2. The apparatus of claim 1 , wherein the first barrier metal layer and the second barrier metal layer are composed of the same material.

3. The apparatus of claim 1 , wherein the first barrier metal layer and the second barrier metal layer are composed of at least one of Ta and TiN.

4. The apparatus of claim 1 , wherein the dielectric layer is formed of a material selected from a group consisting of SiN, SiO 2 , Al 2 O 3 and HfO 2 .

5. The apparatus of claim 1 , wherein:

the lower electrode line further includes a first copper seed layer interposed between the first barrier metal layer and the second barrier metal layer;

the capacitor further includes the first copper seed layer interposed between the first barrier metal layer and the dielectric layer.

6. A method comprising:

providing a semiconductor layer having a lower line formed therein;

forming a first interlayer insulating layer over the semiconductor substrate;

forming a first conductor and a second conductor in the first interlayer insulating layer, the first conductor and the second conductor each being electrically connected to the lower line;

forming a second interlayer insulating layer over the first interlayer insulating layer;

forming a first via hole and a second via hole in the second interlayer insulating layer to expose the uppermost surfaces of the first conductor and the second conductor;

sequentially forming a first barrier metal layer and a dielectric layer over the second interlayer insulating layer in the first via hole and the second via hole;

etching the dielectric layer of the first via hole; and then

forming an electrode line in the first via hole and a capacitor in the second via hole by forming a second barrier metal layer, a second copper seed layer, and a copper layer over the second interlayer insulating layer in the first via hole and in the second via hole.

7. The method of claim 6 , wherein the lower line is composed of at least one of Ta and TiN.

8. The method of claim 6 , wherein the first interlayer insulating layer and the second interlayer insulating layer are composed of a material selected from a group consisting of SiN, SiO 2 , Al 2 O 3 and HfO 2 .

9. The method of claim 6 , wherein the first conductor and the second conductor are composed of the same material.

10. The method of claim 6 , wherein the first conductor and the second conductor are composed of at least one of Ta and TiN.

11. The method of claim 6 , wherein the first barrier metal layer and the second barrier metal layer are composed of the same material.

12. The method of claim 6 , wherein the first barrier metal layer and the second barrier metal layer are composed of at least one of Ta and TiN.

13. The method of claim 6 , further comprising forming a first copper seed layer after forming the first barrier metal layer.

14. The method of claim 6 , wherein etching the dielectric layer of the first via hole is performed using a photoresist process.

15. The method of claim 6 , wherein the dielectric layer is formed of a material selected from a group consisting of SiN, SiO 2 , Al 2 O 3 and HfO 2 .

16. A method comprising:

forming a lower line formed in a semiconductor substrate;

forming a first interlayer insulating layer over the semiconductor substrate;

forming a second interlayer insulating layer over the first interlayer insulating layer;

forming in the second interlayer insulating layer a first via hole and a second via hole;

forming a lower electrode line in the first via hole electrically connected to the lower line; and then

forming a capacitor in the second via hole electrically connected to the lower line,

wherein the lower electrode includes a first barrier metal layer, a second barrier metal layer, a first copper seed layer, a second copper seed layer, and a copper layer, and the capacitor includes the first barrier metal layer, a dielectric layer, the second barrier metal layer, the first copper seed layer and the second copper seed layer.

17. The method of claim 16 , wherein the lower line is composed of at least one of Ta and TiN.

18. The method of claim 16 , wherein the first interlayer insulating layer and the second interlayer insulating layer are composed of a material selected from a group consisting of SiN, SiO 2 , Al 2 O 3 and HfO 2 .

19. The method of claim 16 , wherein the first barrier metal layer and the second barrier metal layer are composed of at least one of Ta and TiN.

20. The method of claim 16 , wherein the dielectric layer is formed of a material selected from a group consisting of SiN, SiO 2 , Al 2 O 3 and HfO 2 .