SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION METHOD FOR THE SAME

1 . A semiconductor integrated circuit comprising:

an integrated power transistor formed on a semiconductor substrate;

an interlayer insulating film formed on the power transistor;

at least one or more first metal patterns made of a first metal layer formed inside the interlayer insulating film at a position right above the power transistor, for acting as a first electrode of the power transistor;

at least one or more second metal patterns made of the first metal layer for acting as a second electrode of the power transistor;

a single first bus made of a second metal layer formed inside the interlayer insulating film at a position right above the first metal layer, the first bus being electrically connected with the at least one or more first metal patterns;

a single second bus made of the second metal layer, the second bus being electrically connected with the at least one second metal patterns; and

one contact pad provided for each of the first bus and the second bus,

wherein each of the first bus and the second bus has at least one slit.

2 . The circuit of claim 1 , wherein at least one or more contact pads are provided for each of the first bus and the second bus.

3 . The circuit of claim 1 , wherein the power transistor is divided into a plurality of parts with an isolation layer.

4 . The circuit of claim 1 , wherein the slit is formed at edges of each of the first bus and the second bus.

5 . The circuit of claim 1 , wherein the slit is formed inside each of the first bus and the second bus.

6 . The circuit of claim 1 , wherein a plurality of slits are formed at edges of and inside each of the first bus and the second bus.

7 . The circuit of claim 1 , wherein each of the first bus and the second bus is divided into a plurality of parts with the slit,

one contact pad is formed on each of the plurality of divided buses, and

the size of the power transistor is equal to or greater than the size of each of the contact pads on each of the plurality of divided buses as is viewed from top.

8 . A fabrication method for a semiconductor integrated circuit, comprising the steps of:

forming an integrated power transistor on a semiconductor substrate;

forming a first interlayer insulating film on the power transistor;

depositing a first metal layer right above the power transistor via the first interlayer insulating film and then patterning the first metal layer, to form at least one or more first metal patterns acting as a first electrode of the power transistor and at least one or more second metal patterns acting as a second electrode of the power transistor;

forming a second interlayer insulating film on the first interlayer insulating film so as to cover the at least one or more first metal patterns and the at least one or more second metal patterns;

depositing a second metal layer right above the first metal layer via the second interlayer insulating film and then patterning the second metal layer, to form a single first bus electrically connected with the at least one or more first metal patterns and having at least one strip and a single second bus electrically connected with the at least one or more second metal patterns and having at least one strip;

forming a third interlayer insulating film on the second interlayer insulating film so as to cover the first bus and the second bus;

forming one opening through the third interlayer insulating film for each of the first bus and the second bus so as to expose the first bus and the second bus;

placing a contact pad on each of the first bus and the second bus exposed in the opening; and

attaching at least one connection member to the contact pad.

9 . The method of claim 8 , wherein the step of forming one opening comprises the step of forming at least one or more openings through the third interlayer insulating film for each of the first bus and the second bus so as to expose the first bus and the second bus.