Comparator having a preamplifier with power saved while latching data
View Patent ↗In a comparator, a differential amplifier has a pair of transistors receiving a signal to be compared for differential amplification, and a current mirror load circuit for outputting a differential output signal in accordance with the relationship in magnitude of the signal to be compared. A latch circuit has inversion amplifiers for amplifying the differential output signal. One inversion amplifier has its input interconnected to an output of the other inversion amplifier and vice versa. The comparator still further includes a transistor for equalizing signals of the differential amplifier, a transistor for enabling the inversion amplifiers to be active, and a constant current source for reducing a current flowing from a supply voltage to the ground when the inversion amplifiers are active.
1. A comparator comprising:
a differential amplifier including a pair of transistors receiving a signal to be compared for differential amplification, and a current minor load circuit for outputting a differential output signal in accordance with a relationship in magnitude of the signal to be compared; and
a latch circuit including inversion amplifiers for amplifying the differential output signal, one of said inversion amplifiers having an input interconnected to an output of another of said inversion amplifiers,
said differential amplifier reducing, after said latch circuit amplifying the differential output signal, a current flowing through said pair of transistors.
2. The comparator in accordance with claim 1 , wherein said differential amplifier is operative in response to a first clock signal, and said latch circuit is operative in response to a second clock signal different from the first clock signal,
said differential amplifier reducing the current flowing through said pair transistors in response to the first clock signal.
3. The comparator in accordance with claim 1 , wherein said differential amplifier reduces the current flowing through said pair of transistors in response to the differential output signal amplified.
4. The comparator in accordance with claim 1 , wherein
said pair of transistors are of a first conductivity type and have source electrodes interconnected in common to a controlled constant current source,
said current minor load circuit including a first pair of second conductivity type of transistors, each of which has drain and gate electrodes interconnected to each other, the drain electrodes of said first pair of second conductivity type of transistors being interconnected to respective drain electrodes of said pair of transistors,
said current minor load circuit further including a second pair of second conductivity type of transistors having gate electrodes interconnected to the respective gate electrodes of the first pair of second conductivity type of transistors,
said second pair of second conductivity type of transistors having drain electrodes for outputting a differential output signal.
5. The comparator in accordance with claim 4 , wherein said differential amplifier reduces the current flowing said pair of transistor in response to the comparison result signal.